From a878edfef23ca7deb3c0698e8c9b1d674ba86cf0 Mon Sep 17 00:00:00 2001
From: Chih-Min Chao <chihmin.chao@sifive.com>
Date: Sun, 24 May 2020 21:57:26 -0700
Subject: rvv: support [u]i8 type

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
---
 riscv/insns/vfncvt_x_f_w.h | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'riscv/insns/vfncvt_x_f_w.h')

diff --git a/riscv/insns/vfncvt_x_f_w.h b/riscv/insns/vfncvt_x_f_w.h
index 3ddbb87..aed35e6 100644
--- a/riscv/insns/vfncvt_x_f_w.h
+++ b/riscv/insns/vfncvt_x_f_w.h
@@ -1,6 +1,10 @@
 // vfncvt.x.f.w vd, vs2, vm
 VI_VFP_CVT_SCALE
 ({
+  auto vs2 = P.VU.elt<float16_t>(rs2_num, i);
+  P.VU.elt<int8_t>(rd_num, i, true) = f16_to_i8(vs2, STATE.frm, true);
+},
+{
   auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
   P.VU.elt<int16_t>(rd_num, i, true) = f32_to_i16(vs2, STATE.frm, true);
 },
-- 
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