From cd668d2f067d802879a7842bc3bed50fa61b2ead Mon Sep 17 00:00:00 2001 From: Rupert Swarbrick Date: Fri, 18 Feb 2022 12:57:52 +0000 Subject: Split out MINSTRET and MCYCLE Before this change, the MCYCLE CSR was just a proxy for MINSTRET. Similarly, CYCLE was a proxy for INSTRET. This models a machine where every instruction takes exactly one cycle to execute. That's not quite precise enough if you want to do cosimulation: there, you're going to want to MCYCLE to actually match the behaviour of your processor (because you need reads from the relevant CSRs to give the expected result). This commit splits the two CSRs, leaving the other proxy relationships unchanged. The code in processor_t::step() which bumps MINSTRET now bumps MCYCLE by the same amount, maintaining the previous behaviour. Of course, now a cosimulation environment can update the value of MCYCLE to fix things up for multi-cycle instructions after they run. --- riscv/execute.cc | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'riscv/execute.cc') diff --git a/riscv/execute.cc b/riscv/execute.cc index 3f7584e..41a15b7 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -349,6 +349,14 @@ void processor_t::step(size_t n) } state.minstret->bump(instret); + + // By default, bump the MCYCLE register by the same delta. This models a + // machine where each instruction takes exactly one cycle to retire. In a + // cosimulation environment, the RTL might manually update MCYCLE + // separately. It should do that between the end of this step() and the + // start of the next one. + state.mcycle->bump(instret); + n -= instret; } } -- cgit v1.1