From ba10686fd18f3fbb036ca04b906deb57e7d1fe54 Mon Sep 17 00:00:00 2001 From: Weiwei Li Date: Mon, 4 Jul 2022 21:31:09 +0800 Subject: add support for sscofpmf extension v0.5.2 since spike doesn't truly support counting of hardware performance events, only csr related read/write functions is supported currently --- riscv/csrs.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'riscv/csrs.h') diff --git a/riscv/csrs.h b/riscv/csrs.h index acd889c..5503255 100644 --- a/riscv/csrs.h +++ b/riscv/csrs.h @@ -744,4 +744,13 @@ class virtualized_stimecmp_csr_t: public virtualized_csr_t { virtualized_stimecmp_csr_t(processor_t* const proc, csr_t_p orig, csr_t_p virt); virtual void verify_permissions(insn_t insn, bool write) const override; }; + +class scountovf_csr_t: public csr_t { + public: + scountovf_csr_t(processor_t* const proc, const reg_t addr); + virtual void verify_permissions(insn_t insn, bool write) const override; + virtual reg_t read() const noexcept override; + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; +}; #endif -- cgit v1.1