From 84a98f6f718cd482710238042eac3d2b855c6768 Mon Sep 17 00:00:00 2001
From: "soberl@nvidia.com" <soberl@nvidia.com>
Date: Tue, 3 May 2022 19:38:07 -0700
Subject: Implement the new csr mseccfg for ePMP as dummy

---
 riscv/csrs.h | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

(limited to 'riscv/csrs.h')

diff --git a/riscv/csrs.h b/riscv/csrs.h
index fb27ae6..660ddd1 100644
--- a/riscv/csrs.h
+++ b/riscv/csrs.h
@@ -89,6 +89,11 @@ class pmpaddr_csr_t: public csr_t {
   // Is the specified access allowed given the pmpcfg privileges?
   bool access_ok(access_type type, reg_t mode) const noexcept;
 
+  // To check lock bit status from outside like mseccfg
+  bool is_locked() const noexcept {
+    return cfg & PMP_L;
+  }
+
  protected:
   virtual bool unlogged_write(const reg_t val) noexcept override;
  private:
@@ -122,6 +127,17 @@ class pmpcfg_csr_t: public csr_t {
   virtual bool unlogged_write(const reg_t val) noexcept override;
 };
 
+class mseccfg_csr_t: public basic_csr_t {
+ public:
+  mseccfg_csr_t(processor_t* const proc, const reg_t addr);
+  bool get_mml() const noexcept;
+  bool get_mmwp() const noexcept;
+  bool get_rlb() const noexcept;
+ protected:
+  virtual bool unlogged_write(const reg_t val) noexcept override;
+};
+
+typedef std::shared_ptr<mseccfg_csr_t> mseccfg_csr_t_p;
 
 // For CSRs that have a virtualized copy under another name. Each
 // instance of virtualized_csr_t will read/write one of two CSRs,
-- 
cgit v1.1


From fc35f34fd0f5307354cc25ae8018cda62f834e25 Mon Sep 17 00:00:00 2001
From: Ryan Buchner <ryan.buchner@arilinc.com>
Date: Tue, 10 May 2022 15:22:11 -0700
Subject: Change henvcfg csr to a henvcfg_csr_t

To do so implemented henvcfg_csr_t.

henvcfg.PBMTE will be read only 0 if menvcfg.PBMTE = 0.
---
 riscv/csrs.h | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

(limited to 'riscv/csrs.h')

diff --git a/riscv/csrs.h b/riscv/csrs.h
index 660ddd1..f6d2c2c 100644
--- a/riscv/csrs.h
+++ b/riscv/csrs.h
@@ -448,6 +448,20 @@ class masked_csr_t: public basic_csr_t {
 };
 
 
+// henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0
+class henvcfg_csr_t final: public masked_csr_t {
+ public:
+  henvcfg_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init, csr_t_p menvcfg);
+
+  reg_t read() const noexcept override {
+    return (menvcfg->read() | ~MENVCFG_PBMTE) & masked_csr_t::read();
+  }
+
+ private:
+  csr_t_p menvcfg;
+};
+
+
 // For satp and vsatp
 // These are three classes in order to handle the [V]TVM bits permission checks
 class base_atp_csr_t: public basic_csr_t {
-- 
cgit v1.1


From 2aedbdd01911a42565cd6d154f82fa00a66410cd Mon Sep 17 00:00:00 2001
From: Weiwei Li <liweiwei@iscas.ac.cn>
Date: Fri, 1 Jul 2022 16:09:02 +0800
Subject: remove multi blank lines

---
 riscv/csrs.h | 37 -------------------------------------
 1 file changed, 37 deletions(-)

(limited to 'riscv/csrs.h')

diff --git a/riscv/csrs.h b/riscv/csrs.h
index f6d2c2c..ab3cdb7 100644
--- a/riscv/csrs.h
+++ b/riscv/csrs.h
@@ -57,7 +57,6 @@ class csr_t {
 
 typedef std::shared_ptr<csr_t> csr_t_p;
 
-
 // Basic CSRs, with XLEN bits fully readable and writable.
 class basic_csr_t: public csr_t {
  public:
@@ -73,7 +72,6 @@ class basic_csr_t: public csr_t {
   reg_t val;
 };
 
-
 class pmpaddr_csr_t: public csr_t {
  public:
   pmpaddr_csr_t(processor_t* const proc, const reg_t addr);
@@ -174,7 +172,6 @@ class epc_csr_t: public csr_t {
   reg_t val;
 };
 
-
 // For mtvec, stvec, and vstvec
 class tvec_csr_t: public csr_t {
  public:
@@ -187,7 +184,6 @@ class tvec_csr_t: public csr_t {
   reg_t val;
 };
 
-
 // For mcause, scause, and vscause
 class cause_csr_t: public basic_csr_t {
  public:
@@ -196,7 +192,6 @@ class cause_csr_t: public basic_csr_t {
   virtual reg_t read() const noexcept override;
 };
 
-
 // For *status family of CSRs
 class base_status_csr_t: public csr_t {
  public:
@@ -218,7 +213,6 @@ class base_status_csr_t: public csr_t {
 
 typedef std::shared_ptr<base_status_csr_t> base_status_csr_t_p;
 
-
 // For vsstatus, which is its own separate architectural register
 // (unlike sstatus)
 class vsstatus_csr_t final: public base_status_csr_t {
@@ -237,7 +231,6 @@ class vsstatus_csr_t final: public base_status_csr_t {
 
 typedef std::shared_ptr<vsstatus_csr_t> vsstatus_csr_t_p;
 
-
 class mstatus_csr_t final: public base_status_csr_t {
  public:
   mstatus_csr_t(processor_t* const proc, const reg_t addr);
@@ -255,7 +248,6 @@ class mstatus_csr_t final: public base_status_csr_t {
 
 typedef std::shared_ptr<mstatus_csr_t> mstatus_csr_t_p;
 
-
 class mstatush_csr_t: public csr_t {
  public:
   mstatush_csr_t(processor_t* const proc, const reg_t addr, mstatus_csr_t_p mstatus);
@@ -267,7 +259,6 @@ class mstatush_csr_t: public csr_t {
   const reg_t mask;
 };
 
-
 class sstatus_proxy_csr_t final: public base_status_csr_t {
  public:
   sstatus_proxy_csr_t(processor_t* const proc, const reg_t addr, mstatus_csr_t_p mstatus);
@@ -299,7 +290,6 @@ class sstatus_csr_t: public virtualized_csr_t {
 
 typedef std::shared_ptr<sstatus_csr_t> sstatus_csr_t_p;
 
-
 class misa_csr_t final: public basic_csr_t {
  public:
   misa_csr_t(processor_t* const proc, const reg_t addr, const reg_t max_isa);
@@ -320,7 +310,6 @@ class misa_csr_t final: public basic_csr_t {
 
 typedef std::shared_ptr<misa_csr_t> misa_csr_t_p;
 
-
 class mip_or_mie_csr_t: public csr_t {
  public:
   mip_or_mie_csr_t(processor_t* const proc, const reg_t addr);
@@ -335,7 +324,6 @@ class mip_or_mie_csr_t: public csr_t {
   virtual reg_t write_mask() const noexcept = 0;
 };
 
-
 // mip is special because some of the bits are driven by hardware pins
 class mip_csr_t: public mip_or_mie_csr_t {
  public:
@@ -349,7 +337,6 @@ class mip_csr_t: public mip_or_mie_csr_t {
 
 typedef std::shared_ptr<mip_csr_t> mip_csr_t_p;
 
-
 class mie_csr_t: public mip_or_mie_csr_t {
  public:
   mie_csr_t(processor_t* const proc, const reg_t addr);
@@ -359,7 +346,6 @@ class mie_csr_t: public mip_or_mie_csr_t {
 
 typedef std::shared_ptr<mie_csr_t> mie_csr_t_p;
 
-
 // For sip, hip, hvip, vsip, sie, hie, vsie which are all just (masked
 // & shifted) views into mip or mie. Each pair will have one of these
 // objects describing the view, e.g. one for sip+sie, one for hip+hie,
@@ -391,7 +377,6 @@ class generic_int_accessor_t {
 
 typedef std::shared_ptr<generic_int_accessor_t> generic_int_accessor_t_p;
 
-
 // For all CSRs that are simply (masked & shifted) views into mip
 class mip_proxy_csr_t: public csr_t {
  public:
@@ -414,8 +399,6 @@ class mie_proxy_csr_t: public csr_t {
   generic_int_accessor_t_p accr;
 };
 
-
-
 class mideleg_csr_t: public basic_csr_t {
  public:
   mideleg_csr_t(processor_t* const proc, const reg_t addr);
@@ -425,7 +408,6 @@ class mideleg_csr_t: public basic_csr_t {
   virtual bool unlogged_write(const reg_t val) noexcept override;
 };
 
-
 class medeleg_csr_t: public basic_csr_t {
  public:
   medeleg_csr_t(processor_t* const proc, const reg_t addr);
@@ -436,7 +418,6 @@ class medeleg_csr_t: public basic_csr_t {
   const reg_t hypervisor_exceptions;
 };
 
-
 // For CSRs with certain bits hardwired
 class masked_csr_t: public basic_csr_t {
  public:
@@ -447,7 +428,6 @@ class masked_csr_t: public basic_csr_t {
   const reg_t mask;
 };
 
-
 // henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0
 class henvcfg_csr_t final: public masked_csr_t {
  public:
@@ -461,7 +441,6 @@ class henvcfg_csr_t final: public masked_csr_t {
   csr_t_p menvcfg;
 };
 
-
 // For satp and vsatp
 // These are three classes in order to handle the [V]TVM bits permission checks
 class base_atp_csr_t: public basic_csr_t {
@@ -492,7 +471,6 @@ class virtualized_satp_csr_t: public virtualized_csr_t {
   satp_csr_t_p orig_satp;
 };
 
-
 // For minstret and mcycle, which are always 64 bits, but in RV32 are
 // split into high and low halves. The first class always holds the
 // full 64-bit value.
@@ -512,7 +490,6 @@ class wide_counter_csr_t: public csr_t {
 
 typedef std::shared_ptr<wide_counter_csr_t> wide_counter_csr_t_p;
 
-
 // A simple proxy to read/write the upper half of minstret/mcycle
 class counter_top_csr_t: public csr_t {
  public:
@@ -526,7 +503,6 @@ class counter_top_csr_t: public csr_t {
 
 typedef std::shared_ptr<counter_top_csr_t> counter_top_csr_t_p;
 
-
 // For a CSR that is an alias of another
 class proxy_csr_t: public csr_t {
  public:
@@ -538,7 +514,6 @@ class proxy_csr_t: public csr_t {
   csr_t_p delegate;
 };
 
-
 // For a CSR with a fixed, unchanging value
 class const_csr_t: public csr_t {
  public:
@@ -550,7 +525,6 @@ class const_csr_t: public csr_t {
   const reg_t val;
 };
 
-
 // For a CSR that is an unprivileged accessor of a privileged counter
 class counter_proxy_csr_t: public proxy_csr_t {
  public:
@@ -560,7 +534,6 @@ class counter_proxy_csr_t: public proxy_csr_t {
   bool myenable(csr_t_p counteren) const noexcept;
 };
 
-
 // For machine-level CSRs that only exist with Hypervisor
 class hypervisor_csr_t: public basic_csr_t {
  public:
@@ -568,7 +541,6 @@ class hypervisor_csr_t: public basic_csr_t {
   virtual void verify_permissions(insn_t insn, bool write) const override;
 };
 
-
 class hideleg_csr_t: public masked_csr_t {
  public:
   hideleg_csr_t(processor_t* const proc, const reg_t addr, csr_t_p mideleg);
@@ -577,7 +549,6 @@ class hideleg_csr_t: public masked_csr_t {
   csr_t_p mideleg;
 };
 
-
 class hgatp_csr_t: public basic_csr_t {
  public:
   hgatp_csr_t(processor_t* const proc, const reg_t addr);
@@ -586,7 +557,6 @@ class hgatp_csr_t: public basic_csr_t {
   virtual bool unlogged_write(const reg_t val) noexcept override;
 };
 
-
 class tselect_csr_t: public basic_csr_t {
  public:
   tselect_csr_t(processor_t* const proc, const reg_t addr);
@@ -594,7 +564,6 @@ class tselect_csr_t: public basic_csr_t {
   virtual bool unlogged_write(const reg_t val) noexcept override;
 };
 
-
 class tdata1_csr_t: public csr_t {
  public:
   tdata1_csr_t(processor_t* const proc, const reg_t addr);
@@ -620,7 +589,6 @@ class debug_mode_csr_t: public basic_csr_t {
 
 typedef std::shared_ptr<tdata2_csr_t> tdata2_csr_t_p;
 
-
 class dpc_csr_t: public epc_csr_t {
  public:
   dpc_csr_t(processor_t* const proc, const reg_t addr);
@@ -648,7 +616,6 @@ class dcsr_csr_t: public csr_t {
 
 typedef std::shared_ptr<dcsr_csr_t> dcsr_csr_t_p;
 
-
 class float_csr_t final: public masked_csr_t {
  public:
   float_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init);
@@ -659,7 +626,6 @@ class float_csr_t final: public masked_csr_t {
 
 typedef std::shared_ptr<float_csr_t> float_csr_t_p;
 
-
 // For a CSR like FCSR, that is actually a view into multiple
 // underlying registers.
 class composite_csr_t: public csr_t {
@@ -676,7 +642,6 @@ class composite_csr_t: public csr_t {
   const unsigned upper_lsb;
 };
 
-
 class seed_csr_t: public csr_t {
  public:
   seed_csr_t(processor_t* const proc, const reg_t addr);
@@ -686,7 +651,6 @@ class seed_csr_t: public csr_t {
   virtual bool unlogged_write(const reg_t val) noexcept override;
 };
 
-
 class vector_csr_t: public basic_csr_t {
  public:
   vector_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init=0);
@@ -701,7 +665,6 @@ class vector_csr_t: public basic_csr_t {
 
 typedef std::shared_ptr<vector_csr_t> vector_csr_t_p;
 
-
 // For CSRs shared between Vector and P extensions (vxsat)
 class vxsat_csr_t: public masked_csr_t {
  public:
-- 
cgit v1.1


From 9b66f89b8102f032f721fe332819325508aa3b95 Mon Sep 17 00:00:00 2001
From: Weiwei Li <liweiwei@iscas.ac.cn>
Date: Wed, 6 Jul 2022 10:43:57 +0800
Subject: modify mstatush_csr_t to general rv32_high_csr_t

---
 riscv/csrs.h | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

(limited to 'riscv/csrs.h')

diff --git a/riscv/csrs.h b/riscv/csrs.h
index ab3cdb7..03a3ed6 100644
--- a/riscv/csrs.h
+++ b/riscv/csrs.h
@@ -53,6 +53,8 @@ class csr_t {
  private:
   const unsigned csr_priv;
   const bool csr_read_only;
+
+  friend class rv32_high_csr_t;
 };
 
 typedef std::shared_ptr<csr_t> csr_t_p;
@@ -243,19 +245,19 @@ class mstatus_csr_t final: public base_status_csr_t {
   virtual bool unlogged_write(const reg_t val) noexcept override;
  private:
   reg_t val;
-  friend class mstatush_csr_t;
 };
 
 typedef std::shared_ptr<mstatus_csr_t> mstatus_csr_t_p;
 
-class mstatush_csr_t: public csr_t {
+class rv32_high_csr_t: public csr_t {
  public:
-  mstatush_csr_t(processor_t* const proc, const reg_t addr, mstatus_csr_t_p mstatus);
+  rv32_high_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, csr_t_p orig);
   virtual reg_t read() const noexcept override;
+  virtual void verify_permissions(insn_t insn, bool write) const override;
  protected:
   virtual bool unlogged_write(const reg_t val) noexcept override;
  private:
-  mstatus_csr_t_p mstatus;
+  csr_t_p orig;
   const reg_t mask;
 };
 
-- 
cgit v1.1


From 2bf74857f0f7f3a63e029d7c7ecaf3d4523a846e Mon Sep 17 00:00:00 2001
From: Weiwei Li <liweiwei@iscas.ac.cn>
Date: Wed, 6 Jul 2022 10:45:04 +0800
Subject: add support for csrs of smstateen extensions

---
 riscv/csrs.h | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

(limited to 'riscv/csrs.h')

diff --git a/riscv/csrs.h b/riscv/csrs.h
index 03a3ed6..15f868c 100644
--- a/riscv/csrs.h
+++ b/riscv/csrs.h
@@ -676,4 +676,23 @@ class vxsat_csr_t: public masked_csr_t {
   virtual bool unlogged_write(const reg_t val) noexcept override;
 };
 
+class hstateen_csr_t: public masked_csr_t {
+ public:
+  hstateen_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init, uint8_t index);
+  virtual reg_t read() const noexcept override;
+  virtual void verify_permissions(insn_t insn, bool write) const override;
+ protected:
+  virtual bool unlogged_write(const reg_t val) noexcept override;
+protected:
+  uint8_t index;
+};
+
+class sstateen_csr_t: public hstateen_csr_t {
+ public:
+  sstateen_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init, uint8_t index);
+  virtual reg_t read() const noexcept override;
+  virtual void verify_permissions(insn_t insn, bool write) const override;
+ protected:
+  virtual bool unlogged_write(const reg_t val) noexcept override;
+};
 #endif
-- 
cgit v1.1


From 11dacaedc4b55ac1d79f1152a549ab9bfb170d2d Mon Sep 17 00:00:00 2001
From: Weiwei Li <liweiwei@iscas.ac.cn>
Date: Wed, 6 Jul 2022 10:51:36 +0800
Subject: add standalone class for fcsr and senvcfg csr

---
 riscv/csrs.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

(limited to 'riscv/csrs.h')

diff --git a/riscv/csrs.h b/riscv/csrs.h
index 15f868c..2b8a2fb 100644
--- a/riscv/csrs.h
+++ b/riscv/csrs.h
@@ -695,4 +695,15 @@ class sstateen_csr_t: public hstateen_csr_t {
  protected:
   virtual bool unlogged_write(const reg_t val) noexcept override;
 };
+
+class fcsr_csr_t: public composite_csr_t {
+ public:
+  fcsr_csr_t(processor_t* const proc, const reg_t addr, csr_t_p upper_csr, csr_t_p lower_csr, const unsigned upper_lsb);
+};
+
+class senvcfg_csr_t final: public masked_csr_t {
+ public:
+  senvcfg_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init);
+};
+
 #endif
-- 
cgit v1.1


From 10fefa1542756a7f7caf45670a64d965a995153a Mon Sep 17 00:00:00 2001
From: Weiwei Li <liweiwei@iscas.ac.cn>
Date: Wed, 6 Jul 2022 10:52:15 +0800
Subject: add smstateen check for fcsr, senvcfg, henvcfg

---
 riscv/csrs.h | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'riscv/csrs.h')

diff --git a/riscv/csrs.h b/riscv/csrs.h
index 2b8a2fb..bde31da 100644
--- a/riscv/csrs.h
+++ b/riscv/csrs.h
@@ -439,6 +439,8 @@ class henvcfg_csr_t final: public masked_csr_t {
     return (menvcfg->read() | ~MENVCFG_PBMTE) & masked_csr_t::read();
   }
 
+  virtual void verify_permissions(insn_t insn, bool write) const override;
+
  private:
   csr_t_p menvcfg;
 };
@@ -699,11 +701,13 @@ class sstateen_csr_t: public hstateen_csr_t {
 class fcsr_csr_t: public composite_csr_t {
  public:
   fcsr_csr_t(processor_t* const proc, const reg_t addr, csr_t_p upper_csr, csr_t_p lower_csr, const unsigned upper_lsb);
+  virtual void verify_permissions(insn_t insn, bool write) const override;
 };
 
 class senvcfg_csr_t final: public masked_csr_t {
  public:
   senvcfg_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init);
+  virtual void verify_permissions(insn_t insn, bool write) const override;
 };
 
 #endif
-- 
cgit v1.1


From e050da4c27635a22d6dbdab920371012b2ea8b4f Mon Sep 17 00:00:00 2001
From: YenHaoChen <howard25336284@gmail.com>
Date: Wed, 13 Jul 2022 09:23:18 +0800
Subject: Add verify_permissions() for mseccfg_csr_t

The mseccfg only exists when enabling the Smepmp extension. If not
enabling the Smepmp extension, CSR instructions to the mseccfg raise
illegal instruction faults, and the PMP behaviors as hardwiring mseccfg
0 (the reset value of mseccfg).
---
 riscv/csrs.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'riscv/csrs.h')

diff --git a/riscv/csrs.h b/riscv/csrs.h
index bde31da..6c7c47d 100644
--- a/riscv/csrs.h
+++ b/riscv/csrs.h
@@ -130,6 +130,7 @@ class pmpcfg_csr_t: public csr_t {
 class mseccfg_csr_t: public basic_csr_t {
  public:
   mseccfg_csr_t(processor_t* const proc, const reg_t addr);
+  virtual void verify_permissions(insn_t insn, bool write) const override;
   bool get_mml() const noexcept;
   bool get_mmwp() const noexcept;
   bool get_rlb() const noexcept;
-- 
cgit v1.1


From 00c38fdb95dff4e18ed75361da03436075a03b3a Mon Sep 17 00:00:00 2001
From: Scott Johnson <scott.johnson@arilinc.com>
Date: Wed, 13 Jul 2022 09:01:15 -0700
Subject: Remove unnecessary mask from rv32_high_csr_t constructor

---
 riscv/csrs.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'riscv/csrs.h')

diff --git a/riscv/csrs.h b/riscv/csrs.h
index bde31da..7b1f87c 100644
--- a/riscv/csrs.h
+++ b/riscv/csrs.h
@@ -251,14 +251,14 @@ typedef std::shared_ptr<mstatus_csr_t> mstatus_csr_t_p;
 
 class rv32_high_csr_t: public csr_t {
  public:
-  rv32_high_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, csr_t_p orig);
+  rv32_high_csr_t(processor_t* const proc, const reg_t addr, csr_t_p orig);
   virtual reg_t read() const noexcept override;
   virtual void verify_permissions(insn_t insn, bool write) const override;
  protected:
   virtual bool unlogged_write(const reg_t val) noexcept override;
  private:
   csr_t_p orig;
-  const reg_t mask;
+  const reg_t mask = -1;
 };
 
 class sstatus_proxy_csr_t final: public base_status_csr_t {
-- 
cgit v1.1


From 8f36f1a5f8a47282743706e7777a277b9f17ba6f Mon Sep 17 00:00:00 2001
From: Scott Johnson <scott.johnson@arilinc.com>
Date: Wed, 13 Jul 2022 09:14:05 -0700
Subject: Remove no-longer-needed mask from rv32_high_csr_t

---
 riscv/csrs.h | 1 -
 1 file changed, 1 deletion(-)

(limited to 'riscv/csrs.h')

diff --git a/riscv/csrs.h b/riscv/csrs.h
index 7b1f87c..3998d79 100644
--- a/riscv/csrs.h
+++ b/riscv/csrs.h
@@ -258,7 +258,6 @@ class rv32_high_csr_t: public csr_t {
   virtual bool unlogged_write(const reg_t val) noexcept override;
  private:
   csr_t_p orig;
-  const reg_t mask = -1;
 };
 
 class sstatus_proxy_csr_t final: public base_status_csr_t {
-- 
cgit v1.1


From 85ab2228ddb802c33a967349d69b2d948846bd01 Mon Sep 17 00:00:00 2001
From: Scott Johnson <scott.johnson@arilinc.com>
Date: Wed, 13 Jul 2022 09:33:36 -0700
Subject: Add proxy for accessing the low 32 bits of a 64-bit CSR

Use this for mstatus on RV32 so that `csrw mstatus` does not modify
the bits in `mstatush`. Fixes #1044.
---
 riscv/csrs.h | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

(limited to 'riscv/csrs.h')

diff --git a/riscv/csrs.h b/riscv/csrs.h
index 3998d79..500bde7 100644
--- a/riscv/csrs.h
+++ b/riscv/csrs.h
@@ -54,7 +54,9 @@ class csr_t {
   const unsigned csr_priv;
   const bool csr_read_only;
 
+  // For access to written_value() and unlogged_write():
   friend class rv32_high_csr_t;
+  friend class rv32_low_csr_t;
 };
 
 typedef std::shared_ptr<csr_t> csr_t_p;
@@ -249,6 +251,19 @@ class mstatus_csr_t final: public base_status_csr_t {
 
 typedef std::shared_ptr<mstatus_csr_t> mstatus_csr_t_p;
 
+// For RV32 CSRs that are split into two, e.g. mstatus/mstatush
+// CSRW should only modify the lower half
+class rv32_low_csr_t: public csr_t {
+ public:
+  rv32_low_csr_t(processor_t* const proc, const reg_t addr, csr_t_p orig);
+  virtual reg_t read() const noexcept override;
+  virtual void verify_permissions(insn_t insn, bool write) const override;
+ protected:
+  virtual bool unlogged_write(const reg_t val) noexcept override;
+ private:
+  csr_t_p orig;
+};
+
 class rv32_high_csr_t: public csr_t {
  public:
   rv32_high_csr_t(processor_t* const proc, const reg_t addr, csr_t_p orig);
-- 
cgit v1.1


From 61a2c0ee6306562e084b25e4734d6ae725c475b4 Mon Sep 17 00:00:00 2001
From: Weiwei Li <liweiwei@iscas.ac.cn>
Date: Sun, 17 Jul 2022 09:13:06 +0800
Subject: extract the progress of computing the inital value of mstatus into
 separate function compute_mstatus_initial_value()

---
 riscv/csrs.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'riscv/csrs.h')

diff --git a/riscv/csrs.h b/riscv/csrs.h
index 500bde7..ea6d4d9 100644
--- a/riscv/csrs.h
+++ b/riscv/csrs.h
@@ -246,6 +246,7 @@ class mstatus_csr_t final: public base_status_csr_t {
  protected:
   virtual bool unlogged_write(const reg_t val) noexcept override;
  private:
+  reg_t compute_mstatus_initial_value() const noexcept;
   reg_t val;
 };
 
-- 
cgit v1.1


From 28ee0c4d6a1ed221f1a05ba48f54023ac7d455cc Mon Sep 17 00:00:00 2001
From: Weiwei Li <liweiwei@iscas.ac.cn>
Date: Fri, 8 Jul 2022 18:34:13 +0800
Subject: modify minstret/mcycle/minstreth/mcycleh to reuse rv32_low/high_csr_t

---
 riscv/csrs.h | 16 ++--------------
 1 file changed, 2 insertions(+), 14 deletions(-)

(limited to 'riscv/csrs.h')

diff --git a/riscv/csrs.h b/riscv/csrs.h
index 500bde7..8108d1e 100644
--- a/riscv/csrs.h
+++ b/riscv/csrs.h
@@ -260,6 +260,7 @@ class rv32_low_csr_t: public csr_t {
   virtual void verify_permissions(insn_t insn, bool write) const override;
  protected:
   virtual bool unlogged_write(const reg_t val) noexcept override;
+  virtual reg_t written_value() const noexcept override;
  private:
   csr_t_p orig;
 };
@@ -271,6 +272,7 @@ class rv32_high_csr_t: public csr_t {
   virtual void verify_permissions(insn_t insn, bool write) const override;
  protected:
   virtual bool unlogged_write(const reg_t val) noexcept override;
+  virtual reg_t written_value() const noexcept override;
  private:
   csr_t_p orig;
 };
@@ -498,7 +500,6 @@ class wide_counter_csr_t: public csr_t {
   // Always returns full 64-bit value
   virtual reg_t read() const noexcept override;
   void bump(const reg_t howmuch) noexcept;
-  void write_upper_half(const reg_t val) noexcept;
  protected:
   virtual bool unlogged_write(const reg_t val) noexcept override;
   virtual reg_t written_value() const noexcept override;
@@ -508,19 +509,6 @@ class wide_counter_csr_t: public csr_t {
 
 typedef std::shared_ptr<wide_counter_csr_t> wide_counter_csr_t_p;
 
-// A simple proxy to read/write the upper half of minstret/mcycle
-class counter_top_csr_t: public csr_t {
- public:
-  counter_top_csr_t(processor_t* const proc, const reg_t addr, wide_counter_csr_t_p parent);
-  virtual reg_t read() const noexcept override;
- protected:
-  virtual bool unlogged_write(const reg_t val) noexcept override;
- private:
-  wide_counter_csr_t_p parent;
-};
-
-typedef std::shared_ptr<counter_top_csr_t> counter_top_csr_t_p;
-
 // For a CSR that is an alias of another
 class proxy_csr_t: public csr_t {
  public:
-- 
cgit v1.1


From 3ff1b5f1c6c6e13777be1c677abc2340f3dabd1a Mon Sep 17 00:00:00 2001
From: Weiwei Li <liweiwei@iscas.ac.cn>
Date: Fri, 8 Jul 2022 20:30:02 +0800
Subject: add support for time/timeh/htimedelta/htimedeltah csrs

---
 riscv/csrs.h | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

(limited to 'riscv/csrs.h')

diff --git a/riscv/csrs.h b/riscv/csrs.h
index 8108d1e..34bc9d0 100644
--- a/riscv/csrs.h
+++ b/riscv/csrs.h
@@ -509,6 +509,21 @@ class wide_counter_csr_t: public csr_t {
 
 typedef std::shared_ptr<wide_counter_csr_t> wide_counter_csr_t_p;
 
+class time_counter_csr_t: public csr_t {
+ public:
+  time_counter_csr_t(processor_t* const proc, const reg_t addr);
+  virtual reg_t read() const noexcept override;
+
+  void sync(const reg_t val) noexcept;
+
+ protected:
+  virtual bool unlogged_write(const reg_t val) noexcept override { return false; };
+ private:
+  reg_t shadow_val;
+};
+
+typedef std::shared_ptr<time_counter_csr_t> time_counter_csr_t_p;
+
 // For a CSR that is an alias of another
 class proxy_csr_t: public csr_t {
  public:
-- 
cgit v1.1


From eb2cce0c99075f89e77b0c1db92108f9c49ccab0 Mon Sep 17 00:00:00 2001
From: Weiwei Li <liweiwei@iscas.ac.cn>
Date: Wed, 3 Aug 2022 10:32:51 +0800
Subject: add stateen related check to frm/fflags and then apply to fcsr
 implicitly

---
 riscv/csrs.h | 6 ------
 1 file changed, 6 deletions(-)

(limited to 'riscv/csrs.h')

diff --git a/riscv/csrs.h b/riscv/csrs.h
index c979942..5fc3a49 100644
--- a/riscv/csrs.h
+++ b/riscv/csrs.h
@@ -717,12 +717,6 @@ class sstateen_csr_t: public hstateen_csr_t {
   virtual bool unlogged_write(const reg_t val) noexcept override;
 };
 
-class fcsr_csr_t: public composite_csr_t {
- public:
-  fcsr_csr_t(processor_t* const proc, const reg_t addr, csr_t_p upper_csr, csr_t_p lower_csr, const unsigned upper_lsb);
-  virtual void verify_permissions(insn_t insn, bool write) const override;
-};
-
 class senvcfg_csr_t final: public masked_csr_t {
  public:
   senvcfg_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init);
-- 
cgit v1.1


From 5672c4a41ad7a9af011d385962c175a5a6012fd9 Mon Sep 17 00:00:00 2001
From: i2h2 <110197402+i2h2@users.noreply.github.com>
Date: Wed, 3 Aug 2022 16:01:57 -0600
Subject: Add Sstc support. (#1057)

---
 riscv/csrs.h | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

(limited to 'riscv/csrs.h')

diff --git a/riscv/csrs.h b/riscv/csrs.h
index c979942..acd889c 100644
--- a/riscv/csrs.h
+++ b/riscv/csrs.h
@@ -449,12 +449,13 @@ class masked_csr_t: public basic_csr_t {
 };
 
 // henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0
+// henvcfg.stce is read_only 0 when menvcfg.stce = 0
 class henvcfg_csr_t final: public masked_csr_t {
  public:
   henvcfg_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init, csr_t_p menvcfg);
 
   reg_t read() const noexcept override {
-    return (menvcfg->read() | ~MENVCFG_PBMTE) & masked_csr_t::read();
+    return (menvcfg->read() | ~(MENVCFG_PBMTE | MENVCFG_STCE)) & masked_csr_t::read();
   }
 
   virtual void verify_permissions(insn_t insn, bool write) const override;
@@ -729,4 +730,18 @@ class senvcfg_csr_t final: public masked_csr_t {
   virtual void verify_permissions(insn_t insn, bool write) const override;
 };
 
+class stimecmp_csr_t: public basic_csr_t {
+ public:
+  stimecmp_csr_t(processor_t* const proc, const reg_t addr, const reg_t imask);
+ protected:
+  virtual bool unlogged_write(const reg_t val) noexcept override;
+ private:
+  reg_t intr_mask;
+};
+
+class virtualized_stimecmp_csr_t: public virtualized_csr_t {
+ public:
+  virtualized_stimecmp_csr_t(processor_t* const proc, csr_t_p orig, csr_t_p virt);
+  virtual void verify_permissions(insn_t insn, bool write) const override;
+};
 #endif
-- 
cgit v1.1


From ba10686fd18f3fbb036ca04b906deb57e7d1fe54 Mon Sep 17 00:00:00 2001
From: Weiwei Li <liweiwei@iscas.ac.cn>
Date: Mon, 4 Jul 2022 21:31:09 +0800
Subject: add support for sscofpmf extension v0.5.2

since spike doesn't truly support counting of hardware performance events,
only csr related read/write functions is supported currently
---
 riscv/csrs.h | 9 +++++++++
 1 file changed, 9 insertions(+)

(limited to 'riscv/csrs.h')

diff --git a/riscv/csrs.h b/riscv/csrs.h
index acd889c..5503255 100644
--- a/riscv/csrs.h
+++ b/riscv/csrs.h
@@ -744,4 +744,13 @@ class virtualized_stimecmp_csr_t: public virtualized_csr_t {
   virtualized_stimecmp_csr_t(processor_t* const proc, csr_t_p orig, csr_t_p virt);
   virtual void verify_permissions(insn_t insn, bool write) const override;
 };
+
+class scountovf_csr_t: public csr_t {
+ public:
+  scountovf_csr_t(processor_t* const proc, const reg_t addr);
+  virtual void verify_permissions(insn_t insn, bool write) const override;
+  virtual reg_t read() const noexcept override;
+ protected:
+  virtual bool unlogged_write(const reg_t val) noexcept override;
+};
 #endif
-- 
cgit v1.1


From ac117cc35aa2bc5296f7a7bfd817a539e269919f Mon Sep 17 00:00:00 2001
From: Greg Chadwick <gac@lowrisc.org>
Date: Thu, 11 Aug 2022 21:09:57 +0100
Subject: Unify PMPCFGx behaviour with PMPADDRx where PMP is disabled (#1068)

Previously any access to the PMPADDRx CSRs when no PMP regions were
configured would result in an illegal instruction trap, whilst
PMPCFGx registers would act as WARL, ignoring writes and reading as 0.

This unifies the behaviour so both PMPADDRx and PMPCFGx CSRs produce an
illegal instruction trap when accessed when no PMP regions are
configured.
---
 riscv/csrs.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'riscv/csrs.h')

diff --git a/riscv/csrs.h b/riscv/csrs.h
index 85a4d50..cabd61e 100644
--- a/riscv/csrs.h
+++ b/riscv/csrs.h
@@ -124,6 +124,7 @@ typedef std::shared_ptr<pmpaddr_csr_t> pmpaddr_csr_t_p;
 class pmpcfg_csr_t: public csr_t {
  public:
   pmpcfg_csr_t(processor_t* const proc, const reg_t addr);
+  virtual void verify_permissions(insn_t insn, bool write) const override;
   virtual reg_t read() const noexcept override;
  protected:
   virtual bool unlogged_write(const reg_t val) noexcept override;
-- 
cgit v1.1


From 8f511653940cb2b9edd9a18ec30a51422b34a573 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Thu, 22 Sep 2022 14:57:42 -0700
Subject: Fix remaining ignored-qualifiers warning

---
 riscv/csrs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'riscv/csrs.h')

diff --git a/riscv/csrs.h b/riscv/csrs.h
index 5dc6da3..1cc2d74 100644
--- a/riscv/csrs.h
+++ b/riscv/csrs.h
@@ -326,7 +326,7 @@ class misa_csr_t final: public basic_csr_t {
  private:
   const reg_t max_isa;
   const reg_t write_mask;
-  const reg_t dependency(const reg_t val, const char feature, const char depends_on) const noexcept;
+  reg_t dependency(const reg_t val, const char feature, const char depends_on) const noexcept;
 };
 
 typedef std::shared_ptr<misa_csr_t> misa_csr_t_p;
-- 
cgit v1.1


From ce69fb5db97ecf240336b7826dd9dddeb32e5dca Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Thu, 22 Sep 2022 17:34:33 -0700
Subject: Suppress most unused variable warnings

---
 riscv/csrs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'riscv/csrs.h')

diff --git a/riscv/csrs.h b/riscv/csrs.h
index 1cc2d74..70fa2f4 100644
--- a/riscv/csrs.h
+++ b/riscv/csrs.h
@@ -521,7 +521,7 @@ class time_counter_csr_t: public csr_t {
   void sync(const reg_t val) noexcept;
 
  protected:
-  virtual bool unlogged_write(const reg_t val) noexcept override { return false; };
+  virtual bool unlogged_write(const reg_t UNUSED val) noexcept override { return false; };
  private:
   reg_t shadow_val;
 };
-- 
cgit v1.1