From eb2cce0c99075f89e77b0c1db92108f9c49ccab0 Mon Sep 17 00:00:00 2001 From: Weiwei Li Date: Wed, 3 Aug 2022 10:32:51 +0800 Subject: add stateen related check to frm/fflags and then apply to fcsr implicitly --- riscv/csrs.cc | 39 +++++++++++++++------------------------ 1 file changed, 15 insertions(+), 24 deletions(-) (limited to 'riscv/csrs.cc') diff --git a/riscv/csrs.cc b/riscv/csrs.cc index d02212b..4ec404b 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -1198,6 +1198,21 @@ void float_csr_t::verify_permissions(insn_t insn, bool write) const { require_fp; if (!proc->extension_enabled('F')) throw trap_illegal_instruction(insn.bits()); + + if (proc->extension_enabled(EXT_SMSTATEEN) && proc->extension_enabled(EXT_ZFINX)) { + if ((state->prv < PRV_M) && !(state->mstateen[0]->read() & MSTATEEN0_FCSR)) + throw trap_illegal_instruction(insn.bits()); + + if (state->v && !(state->hstateen[0]->read() & HSTATEEN0_FCSR)) + throw trap_virtual_instruction(insn.bits()); + + if ((proc->extension_enabled('S') && state->prv < PRV_S) && !(state->sstateen[0]->read() & SSTATEEN0_FCSR)) { + if (state->v) + throw trap_virtual_instruction(insn.bits()); + else + throw trap_illegal_instruction(insn.bits()); + } + } } bool float_csr_t::unlogged_write(const reg_t val) noexcept { @@ -1350,30 +1365,6 @@ void sstateen_csr_t::verify_permissions(insn_t insn, bool write) const { throw trap_virtual_instruction(insn.bits()); } -// implement class fcsr_csr_t -fcsr_csr_t::fcsr_csr_t(processor_t* const proc, const reg_t addr, csr_t_p upper_csr, csr_t_p lower_csr, const unsigned upper_lsb): - composite_csr_t(proc, addr, upper_csr, lower_csr, upper_lsb) { -} - -void fcsr_csr_t::verify_permissions(insn_t insn, bool write) const { - composite_csr_t::verify_permissions(insn, write); - - if (proc->extension_enabled(EXT_SMSTATEEN) && proc->extension_enabled(EXT_ZFINX)) { - if ((state->prv < PRV_M) && !(state->mstateen[0]->read() & MSTATEEN0_FCSR)) - throw trap_illegal_instruction(insn.bits()); - - if (state->v && !(state->hstateen[0]->read() & HSTATEEN0_FCSR)) - throw trap_virtual_instruction(insn.bits()); - - if ((proc->extension_enabled('S') && state->prv < PRV_S) && !(state->sstateen[0]->read() & SSTATEEN0_FCSR)) { - if (state->v) - throw trap_virtual_instruction(insn.bits()); - else - throw trap_illegal_instruction(insn.bits()); - } - } -} - // implement class senvcfg_csr_t senvcfg_csr_t::senvcfg_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init): -- cgit v1.1 From a7de776de66a1c1caea8d896e6ff51503b0a46bf Mon Sep 17 00:00:00 2001 From: Weiwei Li Date: Wed, 3 Aug 2022 22:10:17 +0800 Subject: Fix exception type for accessing senvcfg/henvcfg/hstateen Illegal instruciton trap should be raised when accessing senvcfg/ henvcfg/hstateen if related bit of mstateen is zero in VU mode --- riscv/csrs.cc | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'riscv/csrs.cc') diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 4ec404b..875461a 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -1324,10 +1324,9 @@ bool hstateen_csr_t::unlogged_write(const reg_t val) noexcept { } void hstateen_csr_t::verify_permissions(insn_t insn, bool write) const { - masked_csr_t::verify_permissions(insn, write); - if ((state->prv < PRV_M) && !(state->mstateen[index]->read() & MSTATEEN_HSTATEEN)) throw trap_illegal_instruction(insn.bits()); + masked_csr_t::verify_permissions(insn, write); } // implement class sstateen_csr_t @@ -1372,8 +1371,6 @@ senvcfg_csr_t::senvcfg_csr_t(processor_t* const proc, const reg_t addr, const re } void senvcfg_csr_t::verify_permissions(insn_t insn, bool write) const { - masked_csr_t::verify_permissions(insn, write); - if (proc->extension_enabled(EXT_SMSTATEEN)) { if ((state->prv < PRV_M) && !(state->mstateen[0]->read() & MSTATEEN0_HENVCFG)) throw trap_illegal_instruction(insn.bits()); @@ -1381,13 +1378,15 @@ void senvcfg_csr_t::verify_permissions(insn_t insn, bool write) const { if (state->v && !(state->hstateen[0]->read() & HSTATEEN0_SENVCFG)) throw trap_virtual_instruction(insn.bits()); } -} -void henvcfg_csr_t::verify_permissions(insn_t insn, bool write) const { masked_csr_t::verify_permissions(insn, write); +} +void henvcfg_csr_t::verify_permissions(insn_t insn, bool write) const { if (proc->extension_enabled(EXT_SMSTATEEN)) { if ((state->prv < PRV_M) && !(state->mstateen[0]->read() & MSTATEEN0_HENVCFG)) throw trap_illegal_instruction(insn.bits()); } + + masked_csr_t::verify_permissions(insn, write); } -- cgit v1.1