From 61a2c0ee6306562e084b25e4734d6ae725c475b4 Mon Sep 17 00:00:00 2001 From: Weiwei Li Date: Sun, 17 Jul 2022 09:13:06 +0800 Subject: extract the progress of computing the inital value of mstatus into separate function compute_mstatus_initial_value() --- riscv/csrs.cc | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) (limited to 'riscv/csrs.cc') diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 6f8f260..be23a2e 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -466,15 +466,7 @@ bool sstatus_proxy_csr_t::unlogged_write(const reg_t val) noexcept { // implement class mstatus_csr_t mstatus_csr_t::mstatus_csr_t(processor_t* const proc, const reg_t addr): base_status_csr_t(proc, addr), - val(0 - | (proc->extension_enabled_const('U') && (proc->get_const_xlen() != 32) ? set_field((reg_t)0, MSTATUS_UXL, xlen_to_uxl(proc->get_const_xlen())) : 0) - | (proc->extension_enabled_const('S') && (proc->get_const_xlen() != 32) ? set_field((reg_t)0, MSTATUS_SXL, xlen_to_uxl(proc->get_const_xlen())) : 0) - -#ifdef RISCV_ENABLE_DUAL_ENDIAN - | (proc->get_mmu()->is_target_big_endian() ? MSTATUS_UBE | MSTATUS_SBE | MSTATUS_MBE : 0) -#endif - | 0 // initial value for mstatus - ) { + val(compute_mstatus_initial_value()) { } bool mstatus_csr_t::unlogged_write(const reg_t val) noexcept { @@ -497,6 +489,16 @@ bool mstatus_csr_t::unlogged_write(const reg_t val) noexcept { return true; } +reg_t mstatus_csr_t::compute_mstatus_initial_value() const noexcept { + return 0 + | (proc->extension_enabled_const('U') && (proc->get_const_xlen() != 32) ? set_field((reg_t)0, MSTATUS_UXL, xlen_to_uxl(proc->get_const_xlen())) : 0) + | (proc->extension_enabled_const('S') && (proc->get_const_xlen() != 32) ? set_field((reg_t)0, MSTATUS_SXL, xlen_to_uxl(proc->get_const_xlen())) : 0) +#ifdef RISCV_ENABLE_DUAL_ENDIAN + | (proc->get_mmu()->is_target_big_endian() ? MSTATUS_UBE | MSTATUS_SBE | MSTATUS_MBE : 0) +#endif + | 0; // initial value for mstatus +} + // implement class rv32_low_csr_t rv32_low_csr_t::rv32_low_csr_t(processor_t* const proc, const reg_t addr, csr_t_p orig): csr_t(proc, addr), -- cgit v1.1 From f82e54124345f348abaa80ec82d67528a9a8f774 Mon Sep 17 00:00:00 2001 From: Weiwei Li Date: Sun, 17 Jul 2022 09:46:09 +0800 Subject: remove unnecessary ifdef for RISCV_ENABLE_DUAL_ENDIAN the default target endian is always little endian: - mmu::is_target_big_endian() return false - sim_t::get_target_endianness() return memif_endianness_little when RISCV_ENABLE_DUAL_ENDIAN macro is undefined --- riscv/csrs.cc | 2 -- 1 file changed, 2 deletions(-) (limited to 'riscv/csrs.cc') diff --git a/riscv/csrs.cc b/riscv/csrs.cc index be23a2e..c27410c 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -493,9 +493,7 @@ reg_t mstatus_csr_t::compute_mstatus_initial_value() const noexcept { return 0 | (proc->extension_enabled_const('U') && (proc->get_const_xlen() != 32) ? set_field((reg_t)0, MSTATUS_UXL, xlen_to_uxl(proc->get_const_xlen())) : 0) | (proc->extension_enabled_const('S') && (proc->get_const_xlen() != 32) ? set_field((reg_t)0, MSTATUS_SXL, xlen_to_uxl(proc->get_const_xlen())) : 0) -#ifdef RISCV_ENABLE_DUAL_ENDIAN | (proc->get_mmu()->is_target_big_endian() ? MSTATUS_UBE | MSTATUS_SBE | MSTATUS_MBE : 0) -#endif | 0; // initial value for mstatus } -- cgit v1.1 From 89a79b673208a61f7ff16be628955109a742c1ac Mon Sep 17 00:00:00 2001 From: Weiwei Li Date: Sun, 17 Jul 2022 10:00:23 +0800 Subject: Fix the initial value and write mask for mstatus - MPRV is read-only 0 if U-mode is not supported - If U-mode is not supported, UBE is read-only 0 - If S-mode is not supported, SBE is read-only 0 --- riscv/csrs.cc | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'riscv/csrs.cc') diff --git a/riscv/csrs.cc b/riscv/csrs.cc index c27410c..57778c3 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -474,7 +474,8 @@ bool mstatus_csr_t::unlogged_write(const reg_t val) noexcept { const bool has_gva = has_mpv; const reg_t mask = sstatus_write_mask - | MSTATUS_MIE | MSTATUS_MPIE | MSTATUS_MPRV + | MSTATUS_MIE | MSTATUS_MPIE + | (proc->extension_enabled('U') ? MSTATUS_MPRV : 0) | MSTATUS_MPP | MSTATUS_TW | (proc->extension_enabled('S') ? MSTATUS_TSR : 0) | (has_page ? MSTATUS_TVM : 0) @@ -490,10 +491,13 @@ bool mstatus_csr_t::unlogged_write(const reg_t val) noexcept { } reg_t mstatus_csr_t::compute_mstatus_initial_value() const noexcept { + const reg_t big_endian_bits = (proc->extension_enabled_const('U') ? MSTATUS_UBE : 0) + | (proc->extension_enabled_const('S') ? MSTATUS_SBE : 0) + | MSTATUS_MBE; return 0 | (proc->extension_enabled_const('U') && (proc->get_const_xlen() != 32) ? set_field((reg_t)0, MSTATUS_UXL, xlen_to_uxl(proc->get_const_xlen())) : 0) | (proc->extension_enabled_const('S') && (proc->get_const_xlen() != 32) ? set_field((reg_t)0, MSTATUS_SXL, xlen_to_uxl(proc->get_const_xlen())) : 0) - | (proc->get_mmu()->is_target_big_endian() ? MSTATUS_UBE | MSTATUS_SBE | MSTATUS_MBE : 0) + | (proc->get_mmu()->is_target_big_endian() ? big_endian_bits : 0) | 0; // initial value for mstatus } -- cgit v1.1 From c0b3fdcbaba99576393c57607985a0009bb2ebb1 Mon Sep 17 00:00:00 2001 From: Weiwei Li Date: Tue, 12 Jul 2022 23:21:34 +0800 Subject: modify the check for "state->prv >= PRV_M" to "state->prv == PRV_M" prv can never be larger than PRV_M --- riscv/csrs.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'riscv/csrs.cc') diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 57778c3..c43812b 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -885,7 +885,7 @@ satp_csr_t::satp_csr_t(processor_t* const proc, const reg_t addr): void satp_csr_t::verify_permissions(insn_t insn, bool write) const { base_atp_csr_t::verify_permissions(insn, write); if (get_field(state->mstatus->read(), MSTATUS_TVM)) - require(state->prv >= PRV_M); + require(state->prv == PRV_M); } virtualized_satp_csr_t::virtualized_satp_csr_t(processor_t* const proc, satp_csr_t_p orig, csr_t_p virt): -- cgit v1.1