From b6f7b65b659d485990430e5db3b7dc4a6ee94f8f Mon Sep 17 00:00:00 2001 From: Chih-Min Chao Date: Wed, 8 Apr 2020 21:45:32 -0700 Subject: op: update CSR 1. add new hypervisor csr 2. add debug module csr 3. add some new high part register for rv32 Signed-off-by: Chih-Min Chao --- fesvr/dtm.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'fesvr') diff --git a/fesvr/dtm.cc b/fesvr/dtm.cc index 993011d..91cacb2 100644 --- a/fesvr/dtm.cc +++ b/fesvr/dtm.cc @@ -433,11 +433,11 @@ uint64_t dtm_t::modify_csr(unsigned which, uint64_t data, uint32_t type) // need to run more commands to save and restore // S0. uint32_t prog[] = { - CSRRx(WRITE, S0, CSR_DSCRATCH, S0), + CSRRx(WRITE, S0, CSR_DSCRATCH0, S0), LOAD(xlen, S0, X0, data_base), CSRRx(type, S0, which, S0), STORE(xlen, S0, X0, data_base), - CSRRx(WRITE, S0, CSR_DSCRATCH, S0), + CSRRx(WRITE, S0, CSR_DSCRATCH0, S0), EBREAK }; -- cgit v1.1