From 1cfffeda1e8323729e584c904b2ce78681ba0283 Mon Sep 17 00:00:00 2001 From: Yan Date: Sat, 23 Apr 2022 13:46:07 +0800 Subject: Add zknd zkne zknh zksed zksh disassembly support (#979) --- disasm/disasm.cc | 70 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) (limited to 'disasm/disasm.cc') diff --git a/disasm/disasm.cc b/disasm/disasm.cc index 52dede6..d18f089 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -415,6 +415,18 @@ struct : public arg_t { } } p_imm6; +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::to_string((int)insn.bs()); + } +} bs; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::to_string((int)insn.rcon()); + } +} rcon; + typedef struct { reg_t match; reg_t mask; @@ -2022,6 +2034,64 @@ void disassembler_t::add_instructions(const isa_parser_t* isa) if (isa->extension_enabled(EXT_ZICBOZ)) { DISASM_INSN("cbo.zero", cbo_zero, 0, {&xrs1}); } + + if (isa->extension_enabled(EXT_ZKND) || + isa->extension_enabled(EXT_ZKNE)) { + DISASM_INSN("aes64ks1i", aes64ks1i, 0, {&xrd, &xrs1, &rcon}); + DEFINE_RTYPE(aes64ks2); + } + + if (isa->extension_enabled(EXT_ZKND)) { + if(isa->get_max_xlen() == 64) { + DEFINE_RTYPE(aes64ds); + DEFINE_RTYPE(aes64dsm); + DEFINE_R1TYPE(aes64im); + } else if (isa->get_max_xlen() == 32) { + DISASM_INSN("aes32dsi", aes32dsi, 0, {&xrd, &xrs1, &xrs2, &bs}); + DISASM_INSN("aes32dsmi", aes32dsmi, 0, {&xrd, &xrs1, &xrs2, &bs}); + } + } + + if (isa->extension_enabled(EXT_ZKNE)) { + if(isa->get_max_xlen() == 64) { + DEFINE_RTYPE(aes64es); + DEFINE_RTYPE(aes64esm); + } else if (isa->get_max_xlen() == 32) { + DISASM_INSN("aes32esi", aes32esi, 0, {&xrd, &xrs1, &xrs2, &bs}); + DISASM_INSN("aes32esmi", aes32esmi, 0, {&xrd, &xrs1, &xrs2, &bs}); + } + } + + if (isa->extension_enabled(EXT_ZKNH)) { + DEFINE_R1TYPE(sha256sig0); + DEFINE_R1TYPE(sha256sig1); + DEFINE_R1TYPE(sha256sum0); + DEFINE_R1TYPE(sha256sum1); + if(isa->get_max_xlen() == 64) { + DEFINE_R1TYPE(sha512sig0); + DEFINE_R1TYPE(sha512sig1); + DEFINE_R1TYPE(sha512sum0); + DEFINE_R1TYPE(sha512sum1); + } else if (isa->get_max_xlen() == 32) { + DEFINE_RTYPE(sha512sig0h); + DEFINE_RTYPE(sha512sig0l); + DEFINE_RTYPE(sha512sig1h); + DEFINE_RTYPE(sha512sig1l); + DEFINE_RTYPE(sha512sum0r); + DEFINE_RTYPE(sha512sum1r); + } + } + + if (isa->extension_enabled(EXT_ZKSED)) { + DISASM_INSN("sm4ed", sm4ed, 0, {&xrd, &xrs1, &xrs2, &bs}); + DISASM_INSN("sm4ks", sm4ks, 0, {&xrd, &xrs1, &xrs2, &bs}); + } + + if (isa->extension_enabled(EXT_ZKSH)) { + DEFINE_R1TYPE(sm3p0); + DEFINE_R1TYPE(sm3p1); + } + } disassembler_t::disassembler_t(const isa_parser_t *isa) -- cgit v1.1 From 2bf4c8c3dfe9ef7a454b33f70a4611c9118ce405 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 12 May 2022 15:28:47 -0700 Subject: Add missing Q, H, and Svinval extensions to disassembler fallback --- disasm/disasm.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'disasm/disasm.cc') diff --git a/disasm/disasm.cc b/disasm/disasm.cc index d18f089..2fbc1fb 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -2101,7 +2101,7 @@ disassembler_t::disassembler_t(const isa_parser_t *isa) // next-highest priority: other instructions in same base ISA std::string fallback_isa_string = std::string("rv") + std::to_string(isa->get_max_xlen()) + - "gcv_zfh_zba_zbb_zbc_zbs_zkn_zkr_zks_xbitmanip"; + "gqchv_zfh_zba_zbb_zbc_zbs_zkn_zkr_zks_svinval_xbitmanip"; isa_parser_t fallback_isa(fallback_isa_string.c_str(), DEFAULT_PRIV); add_instructions(&fallback_isa); -- cgit v1.1 From 500d987d8750ff7e048c3e2fc0898863beb051cc Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 12 May 2022 16:14:00 -0700 Subject: Add missing Zicbom and Zicbop extensions to disassembler fallback --- disasm/disasm.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'disasm/disasm.cc') diff --git a/disasm/disasm.cc b/disasm/disasm.cc index 2fbc1fb..b627636 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -2101,7 +2101,7 @@ disassembler_t::disassembler_t(const isa_parser_t *isa) // next-highest priority: other instructions in same base ISA std::string fallback_isa_string = std::string("rv") + std::to_string(isa->get_max_xlen()) + - "gqchv_zfh_zba_zbb_zbc_zbs_zkn_zkr_zks_svinval_xbitmanip"; + "gqchv_zfh_zba_zbb_zbc_zbs_zicbom_zicboz_zkn_zkr_zks_svinval_xbitmanip"; isa_parser_t fallback_isa(fallback_isa_string.c_str(), DEFAULT_PRIV); add_instructions(&fallback_isa); -- cgit v1.1 From ff645fb4eb9cd8a957dd8826369de8dd7e1fb8a3 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 13 May 2022 13:57:55 -0700 Subject: Disassemble Zicbop/Zihintpause HINT instructions (#1000) We do not condition them on Zicbop/Zihintpause because, definitionally, all implementations provide them. --- disasm/disasm.cc | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'disasm/disasm.cc') diff --git a/disasm/disasm.cc b/disasm/disasm.cc index b627636..c8e92d6 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -670,6 +670,7 @@ void disassembler_t::add_instructions(const isa_parser_t* isa) #define DEFINE_I0TYPE(name, code) DISASM_INSN(name, code, mask_rs1, {&xrd, &imm}) #define DEFINE_I1TYPE(name, code) DISASM_INSN(name, code, mask_imm, {&xrd, &xrs1}) #define DEFINE_I2TYPE(name, code) DISASM_INSN(name, code, mask_rd | mask_imm, {&xrs1}) + #define DEFINE_PREFETCH(code) DISASM_INSN(#code, code, 0, {&store_address}) #define DEFINE_LTYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &bigimm}) #define DEFINE_BTYPE(code) add_btype_insn(this, #code, match_##code, mask_##code); #define DEFINE_B1TYPE(name, code) add_b1type_insn(this, name, match_##code, mask_##code); @@ -691,6 +692,14 @@ void disassembler_t::add_instructions(const isa_parser_t* isa) add_insn(new disasm_insn_t("unimp", match_csrrw|(CSR_CYCLE<<20), 0xffffffff, {})); add_insn(new disasm_insn_t("c.unimp", 0, 0xffff, {})); + // Following are HINTs, so they must precede their corresponding base-ISA + // instructions. We do not condition them on Zicbop/Zihintpause because, + // definitionally, all implementations provide them. + DEFINE_PREFETCH(prefetch_r); + DEFINE_PREFETCH(prefetch_w); + DEFINE_PREFETCH(prefetch_i); + DEFINE_NOARG(pause); + DEFINE_XLOAD(lb) DEFINE_XLOAD(lbu) DEFINE_XLOAD(lh) -- cgit v1.1 From 78dfe62633ce4fe6e6a70afae04168e1f102b673 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 13 May 2022 13:58:10 -0700 Subject: Fix disassembly of custom instructions that overlap standard ones (#999) Iterate over the instruction chains in reverse order, prioritizing the last call to `disassembler_t::add_insn`. To preserve behavior for the standard instructions, reverse the order in which we add instructions in the `disassembler_t` constructor. Supersedes #995. --- disasm/disasm.cc | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'disasm/disasm.cc') diff --git a/disasm/disasm.cc b/disasm/disasm.cc index c8e92d6..7df39da 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -7,6 +7,8 @@ #include #include #include +// For std::reverse: +#include // Indicates that the next arg (only) is optional. // If the result of converting the next arg to a string is "" @@ -2116,13 +2118,18 @@ disassembler_t::disassembler_t(const isa_parser_t *isa) // finally: instructions with known opcodes but unknown arguments add_unknown_insns(this); + + // Now, reverse the lists, because we search them back-to-front (so that + // custom instructions later added with add_insn have highest priority). + for (size_t i = 0; i < HASH_SIZE+1; i++) + std::reverse(chain[i].begin(), chain[i].end()); } const disasm_insn_t* disassembler_t::probe_once(insn_t insn, size_t idx) const { - for (size_t j = 0; j < chain[idx].size(); j++) - if(*chain[idx][j] == insn) - return chain[idx][j]; + for (auto it = chain[idx].rbegin(); it != chain[idx].rend(); ++it) + if (*(*it) == insn) + return *it; return NULL; } -- cgit v1.1 From 656fa5acf6aef85ae2326309d9bb2cdba69987ef Mon Sep 17 00:00:00 2001 From: liweiwei90 <34847211+liweiwei90@users.noreply.github.com> Date: Tue, 7 Jun 2022 09:28:36 +0800 Subject: update disasm for cbo.* instructions (#1026) --- disasm/disasm.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'disasm/disasm.cc') diff --git a/disasm/disasm.cc b/disasm/disasm.cc index 7df39da..b42bdc2 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -2037,13 +2037,13 @@ void disassembler_t::add_instructions(const isa_parser_t* isa) } if (isa->extension_enabled(EXT_ZICBOM)) { - DISASM_INSN("cbo.clean", cbo_clean, 0, {&xrs1}); - DISASM_INSN("cbo.flush", cbo_flush, 0, {&xrs1}); - DISASM_INSN("cbo.inval", cbo_inval, 0, {&xrs1}); + DISASM_INSN("cbo.clean", cbo_clean, 0, {&base_only_address}); + DISASM_INSN("cbo.flush", cbo_flush, 0, {&base_only_address}); + DISASM_INSN("cbo.inval", cbo_inval, 0, {&base_only_address}); } if (isa->extension_enabled(EXT_ZICBOZ)) { - DISASM_INSN("cbo.zero", cbo_zero, 0, {&xrs1}); + DISASM_INSN("cbo.zero", cbo_zero, 0, {&base_only_address}); } if (isa->extension_enabled(EXT_ZKND) || -- cgit v1.1 From 204f43cf8288550f1070c216e57f16bb45c5f560 Mon Sep 17 00:00:00 2001 From: Kip Walker Date: Wed, 31 Aug 2022 19:07:33 -0700 Subject: Add disassembly support for Zbc instructions (#1076) --- disasm/disasm.cc | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'disasm/disasm.cc') diff --git a/disasm/disasm.cc b/disasm/disasm.cc index b42bdc2..8a03677 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -889,6 +889,12 @@ void disassembler_t::add_instructions(const isa_parser_t* isa) } } + if (isa->extension_enabled(EXT_ZBC)) { + DEFINE_RTYPE(clmul); + DEFINE_RTYPE(clmulh); + DEFINE_RTYPE(clmulr); + } + if (isa->extension_enabled(EXT_ZBS)) { DEFINE_RTYPE(bclr); DEFINE_RTYPE(binv); -- cgit v1.1 From da93bdc435b985fd354e01c26470f64c33cecaa6 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 22 Sep 2022 15:31:08 -0700 Subject: Delete functions that are actually unused --- disasm/disasm.cc | 6 ------ 1 file changed, 6 deletions(-) (limited to 'disasm/disasm.cc') diff --git a/disasm/disasm.cc b/disasm/disasm.cc index 8a03677..7bb3ec0 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -568,11 +568,6 @@ static void NOINLINE add_pitype5_insn(disassembler_t* d, const char* name, uint3 d->add_insn(new disasm_insn_t(name, match, mask, {&xrd, &xrs1, &p_imm5})); } -static void NOINLINE add_pitype6_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) -{ - d->add_insn(new disasm_insn_t(name, match, mask, {&xrd, &xrs1, &p_imm6})); -} - static void NOINLINE add_vector_v_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) { d->add_insn(new disasm_insn_t(name, match, mask, {&vd, &vs2, opt, &vm})); @@ -1684,7 +1679,6 @@ void disassembler_t::add_instructions(const isa_parser_t* isa) #define DEFINE_PI3TYPE(code) add_pitype3_insn(this, #code, match_##code, mask_##code); #define DEFINE_PI4TYPE(code) add_pitype4_insn(this, #code, match_##code, mask_##code); #define DEFINE_PI5TYPE(code) add_pitype5_insn(this, #code, match_##code, mask_##code); -#define DEFINE_PI6TYPE(code) add_pitype6_insn(this, #code, match_##code, mask_##code); #define DISASM_8_AND_16_RINSN(code) \ DEFINE_RTYPE(code##8); \ -- cgit v1.1 From ce69fb5db97ecf240336b7826dd9dddeb32e5dca Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 22 Sep 2022 17:34:33 -0700 Subject: Suppress most unused variable warnings --- disasm/disasm.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'disasm/disasm.cc') diff --git a/disasm/disasm.cc b/disasm/disasm.cc index 7bb3ec0..1d7c6d5 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -180,7 +180,7 @@ struct : public arg_t { } rvc_fp_rs2s; struct : public arg_t { - std::string to_string(insn_t insn) const { + std::string to_string(insn_t UNUSED insn) const { return xpr_name[X_SP]; } } rvc_sp; @@ -314,7 +314,7 @@ struct : public arg_t { } vm; struct : public arg_t { - std::string to_string(insn_t insn) const { + std::string to_string(insn_t UNUSED insn) const { return "v0"; } } v0; @@ -358,7 +358,7 @@ struct : public arg_t { } v_vtype; struct : public arg_t { - std::string to_string(insn_t insn) const { + std::string to_string(insn_t UNUSED insn) const { return "x0"; } } x0; -- cgit v1.1 From 3ee74b7be334d1e2393a134f26de8dfe0cd65feb Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 22 Sep 2022 18:01:19 -0700 Subject: Silence unused-variable warnings in auto-generated code --- disasm/disasm.cc | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'disasm/disasm.cc') diff --git a/disasm/disasm.cc b/disasm/disasm.cc index 1d7c6d5..a8ba91e 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -10,6 +10,10 @@ // For std::reverse: #include +#ifdef __GNUC__ +# pragma GCC diagnostic ignored "-Wunused-variable" +#endif + // Indicates that the next arg (only) is optional. // If the result of converting the next arg to a string is "" // then it will not be printed. -- cgit v1.1 From 8ff186bd0f8446ac6d129fef6836d192f2ce21b1 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 10 Oct 2022 09:31:31 -0700 Subject: Fix disassembly of RV64 srai.u The shift amount is 6 bits wide on RV64. As with the base ISA shifts, we ignore XLEN and unconditionally disassemble the 6-bit immediate on RV32. Partially reverts da93bdc435b985fd354e01c26470f64c33cecaa6 --- disasm/disasm.cc | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'disasm/disasm.cc') diff --git a/disasm/disasm.cc b/disasm/disasm.cc index a8ba91e..856a651 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -572,6 +572,11 @@ static void NOINLINE add_pitype5_insn(disassembler_t* d, const char* name, uint3 d->add_insn(new disasm_insn_t(name, match, mask, {&xrd, &xrs1, &p_imm5})); } +static void NOINLINE add_pitype6_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&xrd, &xrs1, &p_imm6})); +} + static void NOINLINE add_vector_v_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) { d->add_insn(new disasm_insn_t(name, match, mask, {&vd, &vs2, opt, &vm})); @@ -1683,6 +1688,7 @@ void disassembler_t::add_instructions(const isa_parser_t* isa) #define DEFINE_PI3TYPE(code) add_pitype3_insn(this, #code, match_##code, mask_##code); #define DEFINE_PI4TYPE(code) add_pitype4_insn(this, #code, match_##code, mask_##code); #define DEFINE_PI5TYPE(code) add_pitype5_insn(this, #code, match_##code, mask_##code); +#define DEFINE_PI6TYPE(code) add_pitype6_insn(this, #code, match_##code, mask_##code); #define DISASM_8_AND_16_RINSN(code) \ DEFINE_RTYPE(code##8); \ @@ -1921,7 +1927,7 @@ void disassembler_t::add_instructions(const isa_parser_t* isa) DEFINE_RTYPE(msubr32); DEFINE_RTYPE(ave); DEFINE_RTYPE(sra_u); - DEFINE_PI5TYPE(srai_u); + DEFINE_PI6TYPE(srai_u); DEFINE_PI3TYPE(insb); DEFINE_RTYPE(maddr32) -- cgit v1.1