From db762327efe1c754081f7cbfa1f1cae168fedf17 Mon Sep 17 00:00:00 2001 From: YenHaoChen Date: Tue, 11 Jun 2024 09:27:33 +0800 Subject: triggers: implement tcontrol Implement Debug spec Section 5.7.6. Trigger Control (tcontrol). This commit lets tcontrol be read-only 0 if number of triggers is 0. --- riscv/insn_template.h | 1 + riscv/insns/mret.h | 1 + riscv/processor.cc | 4 ++++ riscv/processor.h | 1 + riscv/triggers.cc | 3 ++- 5 files changed, 9 insertions(+), 1 deletion(-) diff --git a/riscv/insn_template.h b/riscv/insn_template.h index 88a41c2..bf9d9d7 100644 --- a/riscv/insn_template.h +++ b/riscv/insn_template.h @@ -8,4 +8,5 @@ #include "specialize.h" #include "tracer.h" #include "v_ext_macros.h" +#include "debug_defines.h" #include diff --git a/riscv/insns/mret.h b/riscv/insns/mret.h index 6d4d59f..3fe920c 100644 --- a/riscv/insns/mret.h +++ b/riscv/insns/mret.h @@ -15,4 +15,5 @@ if (ZICFILP_xLPE(prev_virt, prev_prv)) { s = set_field(s, MSTATUS_MPELP, elp_t::NO_LP_EXPECTED); STATE.mstatus->write(s); if (STATE.mstatush) STATE.mstatush->write(s >> 32); // log mstatush change +STATE.tcontrol->write((STATE.tcontrol->read() & CSR_TCONTROL_MPTE) ? (CSR_TCONTROL_MPTE | CSR_TCONTROL_MTE) : 0); p->set_privilege(prev_prv, prev_virt); diff --git a/riscv/processor.cc b/riscv/processor.cc index da49a37..a1cec6c 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -11,6 +11,7 @@ #include "disasm.h" #include "platform.h" #include "vector_unit.h" +#include "debug_defines.h" #include #include #include @@ -403,11 +404,13 @@ void state_t::reset(processor_t* const proc, reg_t max_isa) csrmap[CSR_TDATA2] = tdata2 = std::make_shared(proc, CSR_TDATA2); csrmap[CSR_TDATA3] = std::make_shared(proc, CSR_TDATA3); csrmap[CSR_TINFO] = std::make_shared(proc, CSR_TINFO); + csrmap[CSR_TCONTROL] = tcontrol = std::make_shared(proc, CSR_TCONTROL, CSR_TCONTROL_MPTE | CSR_TCONTROL_MTE, 0); } else { csrmap[CSR_TDATA1] = std::make_shared(proc, CSR_TDATA1, 0); csrmap[CSR_TDATA2] = tdata2 = std::make_shared(proc, CSR_TDATA2, 0); csrmap[CSR_TDATA3] = std::make_shared(proc, CSR_TDATA3, 0); csrmap[CSR_TINFO] = std::make_shared(proc, CSR_TINFO, 0); + csrmap[CSR_TCONTROL] = tcontrol = std::make_shared(proc, CSR_TCONTROL, 0); } unsigned scontext_length = (xlen == 32 ? 16 : 32); // debug spec suggests 16-bit for RV32 and 32-bit for RV64 csrmap[CSR_SCONTEXT] = scontext = std::make_shared(proc, CSR_SCONTEXT, (reg_t(1) << scontext_length) - 1, 0); @@ -951,6 +954,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc) state.elp = elp_t::NO_LP_EXPECTED; state.mstatus->write(s); if (state.mstatush) state.mstatush->write(s >> 32); // log mstatush change + state.tcontrol->write((state.tcontrol->read() & CSR_TCONTROL_MTE) ? CSR_TCONTROL_MPTE : 0); set_privilege(PRV_M, false); } } diff --git a/riscv/processor.h b/riscv/processor.h index 3e37b43..c03c3ef 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -141,6 +141,7 @@ struct state_t dcsr_csr_t_p dcsr; csr_t_p tselect; csr_t_p tdata2; + csr_t_p tcontrol; csr_t_p scontext; csr_t_p mcontext; diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 1d0ed8b..aa258bd 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -59,7 +59,8 @@ bool trigger_t::common_match(processor_t * const proc, bool use_prev_prv) const auto state = proc->get_state(); auto prv = use_prev_prv ? state->prev_prv : state->prv; auto v = use_prev_prv ? state->prev_v : state->v; - return mode_match(prv, v) && textra_match(proc); + auto m_enabled = get_action() != 0 || (state->tcontrol->read() & CSR_TCONTROL_MTE); + return (prv < PRV_M || m_enabled) && mode_match(prv, v) && textra_match(proc); } bool trigger_t::mode_match(reg_t prv, bool v) const noexcept -- cgit v1.1