From b2ae7abe22e0f0768b4c49d686a93f9c240985da Mon Sep 17 00:00:00 2001
From: "Dave.Wen" <dave.wen@sifive.com>
Date: Thu, 21 May 2020 20:42:07 -0700
Subject: rvv: update the exception rules for v[m]adc/v[m]sbc

---
 riscv/decode.h | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/riscv/decode.h b/riscv/decode.h
index fa96ced..1b844c0 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -475,6 +475,14 @@ static inline bool is_aligned(const unsigned val, const unsigned pos)
   } \
   require_vm; \
 
+#define VI_CHECK_CI_BI(is_vs1) \
+  require_noover(insn.rd(), 1, insn.rs2(), P.VU.vflmul); \
+  require_align(insn.rs2(), P.VU.vflmul); \
+  if (is_vs1) {\
+    require_noover(insn.rd(), 1, insn.rs1(), P.VU.vflmul); \
+    require_align(insn.rs1(), P.VU.vflmul); \
+  }
+
 #define VI_CHECK_MSS(is_vs1) \
   if (P.VU.vflmul > 1) { \
     require_noover(insn.rd(), 1, insn.rs2(), P.VU.vflmul); \
@@ -1366,7 +1374,7 @@ VI_LOOP_END
 
 // carry/borrow bit loop
 #define VI_VV_LOOP_CARRY(BODY) \
-  VI_CHECK_MSS(true); \
+  VI_CHECK_CI_BI(true); \
   VI_GENERAL_LOOP_BASE \
   VI_MASK_VARS \
     if (sew == e8){ \
@@ -1385,7 +1393,7 @@ VI_LOOP_END
   VI_LOOP_END
 
 #define VI_XI_LOOP_CARRY(BODY) \
-  VI_CHECK_MSS(false); \
+  VI_CHECK_CI_BI(false); \
   VI_GENERAL_LOOP_BASE \
   VI_MASK_VARS \
     if (sew == e8){ \
@@ -1404,7 +1412,7 @@ VI_LOOP_END
   VI_LOOP_END
 
 #define VI_VV_LOOP_WITH_CARRY(BODY) \
-  require(P.VU.vflmul == 1 || insn.rd() != 0); \
+  require(insn.rd() != 0); \
   VI_CHECK_SSS(true); \
   VI_GENERAL_LOOP_BASE \
   VI_MASK_VARS \
@@ -1424,7 +1432,7 @@ VI_LOOP_END
   VI_LOOP_END
 
 #define VI_XI_LOOP_WITH_CARRY(BODY) \
-  require(P.VU.vflmul == 1 || insn.rd() != 0); \
+  require(insn.rd() != 0); \
   VI_CHECK_SSS(false); \
   VI_GENERAL_LOOP_BASE \
   VI_MASK_VARS \
-- 
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