From 939128f1e0a10c6c770bf15394d3c8b0606eb059 Mon Sep 17 00:00:00 2001
From: Chih-Min Chao <chihmin.chao@sifive.com>
Date: Tue, 16 Jun 2020 21:07:54 -0700
Subject: zfh: support register dump in interactive mode

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
---
 riscv/interactive.cc | 9 +++++++++
 riscv/sim.h          | 1 +
 2 files changed, 10 insertions(+)

diff --git a/riscv/interactive.cc b/riscv/interactive.cc
index 405bf35..00e505d 100644
--- a/riscv/interactive.cc
+++ b/riscv/interactive.cc
@@ -69,6 +69,7 @@ void sim_t::interactive()
   funcs["vreg"] = &sim_t::interactive_vreg;
   funcs["reg"] = &sim_t::interactive_reg;
   funcs["freg"] = &sim_t::interactive_freg;
+  funcs["fregh"] = &sim_t::interactive_fregh;
   funcs["fregs"] = &sim_t::interactive_fregs;
   funcs["fregd"] = &sim_t::interactive_fregd;
   funcs["pc"] = &sim_t::interactive_pc;
@@ -118,6 +119,7 @@ void sim_t::interactive_help(const std::string& cmd, const std::vector<std::stri
   std::cerr <<
     "Interactive commands:\n"
     "reg <core> [reg]                # Display [reg] (all if omitted) in <core>\n"
+    "fregh <core> <reg>              # Display half precision <reg> in <core>\n"
     "fregs <core> <reg>              # Display single precision <reg> in <core>\n"
     "fregd <core> <reg>              # Display double precision <reg> in <core>\n"
     "vreg <core> [reg]               # Display vector [reg] (all if omitted) in <core>\n"
@@ -296,6 +298,13 @@ void sim_t::interactive_freg(const std::string& cmd, const std::vector<std::stri
   fprintf(stderr, "0x%016" PRIx64 "%016" PRIx64 "\n", r.v[1], r.v[0]);
 }
 
+void sim_t::interactive_fregh(const std::string& cmd, const std::vector<std::string>& args)
+{
+  fpr f;
+  f.r = freg(f16_to_f32(f16(get_freg(args))));
+  fprintf(stderr, "%g\n", isBoxedF32(f.r) ? (double)f.s : NAN);
+}
+
 void sim_t::interactive_fregs(const std::string& cmd, const std::vector<std::string>& args)
 {
   fpr f;
diff --git a/riscv/sim.h b/riscv/sim.h
index eee24e5..7cf83d6 100644
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -105,6 +105,7 @@ private:
   void interactive_vreg(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_reg(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_freg(const std::string& cmd, const std::vector<std::string>& args);
+  void interactive_fregh(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_fregs(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_fregd(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_pc(const std::string& cmd, const std::vector<std::string>& args);
-- 
cgit v1.1


From 0ea56186d527433c21cf76e2d2a6a53a8d9695dc Mon Sep 17 00:00:00 2001
From: Chih-Min Chao <chihmin.chao@sifive.com>
Date: Tue, 16 Jun 2020 21:40:00 -0700
Subject: rvv: disasm: fix vwadd.wx operand

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
---
 spike_main/disasm.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/spike_main/disasm.cc b/spike_main/disasm.cc
index d2947ee..9ab8dd4 100644
--- a/spike_main/disasm.cc
+++ b/spike_main/disasm.cc
@@ -805,7 +805,7 @@ disassembler_t::disassembler_t(int xlen)
   #define DISASM_OPIV_W___INSN(name, sign) \
     add_insn(new disasm_insn_t(#name ".wv", match_##name##_wv, mask_##name##_wv, \
                 {&vd, &vs2, &vs1, &opt, &vm})); \
-    add_insn(new disasm_insn_t(#name ".wx", match_##name##_wv, mask_##name##_wv, \
+    add_insn(new disasm_insn_t(#name ".wx", match_##name##_wx, mask_##name##_wx, \
                 {&vd, &vs2, &xrs1, &opt, &vm}));
 
   #define DISASM_OPIV_M___INSN(name, sign) \
-- 
cgit v1.1