From 75d9ab427d9d9a6039140d899d363cbf170df488 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU>
Date: Fri, 4 Feb 2011 16:09:47 -0800
Subject: [sim,pk] added interrupt-pending field to cause reg

---
 riscv/decode.h      |  5 +++++
 riscv/insns/mtpcr.h |  2 +-
 riscv/processor.cc  | 16 ++++++----------
 riscv/processor.h   |  1 -
 riscv/trap.h        |  2 +-
 5 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/riscv/decode.h b/riscv/decode.h
index 4c30e62..40b8b5e 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -44,6 +44,11 @@ const int JUMP_ALIGN_BITS = 1;
 #define SR_IM_SHIFT 8
 #define TIMER_IRQ 7
 
+#define CAUSE_EXCCODE 0x000000FF
+#define CAUSE_IP      0x0000FF00
+#define CAUSE_EXCCODE_SHIFT 0
+#define CAUSE_IP_SHIFT      8
+
 #define FP_RD_NE  0
 #define FP_RD_0   1
 #define FP_RD_DN  2
diff --git a/riscv/insns/mtpcr.h b/riscv/insns/mtpcr.h
index 1a31a32..449f63d 100644
--- a/riscv/insns/mtpcr.h
+++ b/riscv/insns/mtpcr.h
@@ -15,7 +15,7 @@ switch(insn.rtype.rs2)
     count = RS1;
     break;
   case 5:
-    interrupts_pending &= ~(1 << TIMER_IRQ);
+    cause &= ~(1 << (TIMER_IRQ+CAUSE_IP_SHIFT));
     compare = RS1;
     break;
 
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 6f36653..f5b6de1 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -25,7 +25,6 @@ processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz)
   fromhost = 0;
   count = 0;
   compare = 0;
-  interrupts_pending = 0;
   set_sr(SR_S | SR_SX);  // SX ignored if 64b mode not supported
   set_fsr(0);
 
@@ -70,13 +69,10 @@ void processor_t::step(size_t n, bool noisy)
   {
     for( ; i < n; i++)
     {
-      uint32_t interrupts = interrupts_pending & ((sr & SR_IM) >> SR_IM_SHIFT);
-      if((sr & SR_ET) && interrupts)
-      {
-        for(int i = 0; interrupts; i++, interrupts >>= 1)
-          if(interrupts & 1)
-            throw trap_t(16+i);
-      }
+      uint32_t interrupts = (cause & CAUSE_IP) >> CAUSE_IP_SHIFT;
+      interrupts &= (sr & SR_IM) >> SR_IM_SHIFT;
+      if(interrupts && (sr & SR_ET))
+        take_trap(trap_interrupt,noisy);
 
       insn_t insn = mmu.load_insn(pc);
   
@@ -91,7 +87,7 @@ void processor_t::step(size_t n, bool noisy)
       XPR[0] = 0;
 
       if(count++ == compare)
-        interrupts_pending |= 1 << TIMER_IRQ;
+        cause |= 1 << (TIMER_IRQ+CAUSE_IP_SHIFT);
     }
     return;
   }
@@ -112,7 +108,7 @@ void processor_t::take_trap(trap_t t, bool noisy)
            id, trap_name(t), (unsigned long long)pc);
 
   set_sr((((sr & ~SR_ET) | SR_S) & ~SR_PS) | ((sr & SR_S) ? SR_PS : 0));
-  cause = t;
+  cause = (cause & ~CAUSE_EXCCODE) | (t << CAUSE_EXCCODE_SHIFT);
   epc = pc;
   pc = evec;
   badvaddr = mmu.get_badvaddr();
diff --git a/riscv/processor.h b/riscv/processor.h
index b548038..c1c65ce 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -36,7 +36,6 @@ private:
   uint32_t sr;
   uint32_t count;
   uint32_t compare;
-  uint32_t interrupts_pending;
 
   // unprivileged control registers
   uint32_t fsr;
diff --git a/riscv/trap.h b/riscv/trap.h
index 5ba1183..3af8840 100644
--- a/riscv/trap.h
+++ b/riscv/trap.h
@@ -8,7 +8,7 @@
   DECLARE_TRAP(privileged_instruction), \
   DECLARE_TRAP(fp_disabled), \
   DECLARE_TRAP(syscall), \
-  DECLARE_TRAP(breakpoint), \
+  DECLARE_TRAP(interrupt), \
   DECLARE_TRAP(data_address_misaligned), \
   DECLARE_TRAP(load_access_fault), \
   DECLARE_TRAP(store_access_fault), \
-- 
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