From 74554e7d842df5c4d5b9fc1c7cc0f89ad3d5966e Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Mon, 12 Feb 2018 20:21:38 -0800
Subject: Implement cycleh/instreth CSRs for RV32

---
 riscv/processor.cc | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 516a708..8cca490 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -565,6 +565,11 @@ reg_t processor_t::get_csr(int which)
     case CSR_MINSTRET:
     case CSR_MCYCLE:
       return state.minstret;
+    case CSR_INSTRETH:
+    case CSR_CYCLEH:
+      if (ctr_ok && xlen == 32)
+        return state.minstret >> 32;
+      break;
     case CSR_MINSTRETH:
     case CSR_MCYCLEH:
       if (xlen == 32)
-- 
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