From 08bad17b04320631f2e60af8ea07e04e2af613ac Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Mon, 30 Oct 2023 17:21:40 -0500 Subject: add byte width amo instructions --- riscv/insns/amoadd_b.h | 3 +++ riscv/insns/amoand_b.h | 3 +++ riscv/insns/amocas_b.h | 4 ++++ riscv/insns/amomax_b.h | 3 +++ riscv/insns/amomaxu_b.h | 3 +++ riscv/insns/amomin_b.h | 3 +++ riscv/insns/amominu_b.h | 3 +++ riscv/insns/amoor_b.h | 3 +++ riscv/insns/amoswap_b.h | 3 +++ riscv/insns/amoxor_b.h | 3 +++ 10 files changed, 31 insertions(+) create mode 100644 riscv/insns/amoadd_b.h create mode 100644 riscv/insns/amoand_b.h create mode 100644 riscv/insns/amocas_b.h create mode 100644 riscv/insns/amomax_b.h create mode 100644 riscv/insns/amomaxu_b.h create mode 100644 riscv/insns/amomin_b.h create mode 100644 riscv/insns/amominu_b.h create mode 100644 riscv/insns/amoor_b.h create mode 100644 riscv/insns/amoswap_b.h create mode 100644 riscv/insns/amoxor_b.h diff --git a/riscv/insns/amoadd_b.h b/riscv/insns/amoadd_b.h new file mode 100644 index 0000000..2138104 --- /dev/null +++ b/riscv/insns/amoadd_b.h @@ -0,0 +1,3 @@ +require_extension('A'); +require_extension(EXT_ZABHA); +WRITE_RD((sreg_t)(int8_t)(MMU.amo(RS1, [&](uint8_t lhs) { return lhs + RS2; }))); diff --git a/riscv/insns/amoand_b.h b/riscv/insns/amoand_b.h new file mode 100644 index 0000000..f461c29 --- /dev/null +++ b/riscv/insns/amoand_b.h @@ -0,0 +1,3 @@ +require_extension('A'); +require_extension(EXT_ZABHA); +WRITE_RD((sreg_t)(int8_t)(MMU.amo(RS1, [&](uint8_t lhs) { return lhs & RS2; }))); diff --git a/riscv/insns/amocas_b.h b/riscv/insns/amocas_b.h new file mode 100644 index 0000000..ca609c7 --- /dev/null +++ b/riscv/insns/amocas_b.h @@ -0,0 +1,4 @@ +require_extension('A'); +require_extension(EXT_ZACAS); +require_extension(EXT_ZABHA); +WRITE_RD((sreg_t)(int8_t)(MMU.amo_compare_and_swap(RS1, RD, RS2))); diff --git a/riscv/insns/amomax_b.h b/riscv/insns/amomax_b.h new file mode 100644 index 0000000..8187a3c --- /dev/null +++ b/riscv/insns/amomax_b.h @@ -0,0 +1,3 @@ +require_extension('A'); +require_extension(EXT_ZABHA); +WRITE_RD((sreg_t)(int8_t)(MMU.amo(RS1, [&](int8_t lhs) { return std::max(lhs, int8_t(RS2)); }))); diff --git a/riscv/insns/amomaxu_b.h b/riscv/insns/amomaxu_b.h new file mode 100644 index 0000000..534b3ca --- /dev/null +++ b/riscv/insns/amomaxu_b.h @@ -0,0 +1,3 @@ +require_extension('A'); +require_extension(EXT_ZABHA); +WRITE_RD((sreg_t)(int8_t)(MMU.amo(RS1, [&](uint8_t lhs) { return std::max(lhs, uint8_t(RS2)); }))); diff --git a/riscv/insns/amomin_b.h b/riscv/insns/amomin_b.h new file mode 100644 index 0000000..c5e8cf9 --- /dev/null +++ b/riscv/insns/amomin_b.h @@ -0,0 +1,3 @@ +require_extension('A'); +require_extension(EXT_ZABHA); +WRITE_RD((sreg_t)(int8_t)(MMU.amo(RS1, [&](int8_t lhs) { return std::min(lhs, int8_t(RS2)); }))); diff --git a/riscv/insns/amominu_b.h b/riscv/insns/amominu_b.h new file mode 100644 index 0000000..9bce0e7 --- /dev/null +++ b/riscv/insns/amominu_b.h @@ -0,0 +1,3 @@ +require_extension('A'); +require_extension(EXT_ZABHA); +WRITE_RD((sreg_t)(int8_t)(MMU.amo(RS1, [&](uint8_t lhs) { return std::min(lhs, uint8_t(RS2)); }))); diff --git a/riscv/insns/amoor_b.h b/riscv/insns/amoor_b.h new file mode 100644 index 0000000..f96ff54 --- /dev/null +++ b/riscv/insns/amoor_b.h @@ -0,0 +1,3 @@ +require_extension('A'); +require_extension(EXT_ZABHA); +WRITE_RD((sreg_t)(int8_t)(MMU.amo(RS1, [&](uint8_t lhs) { return lhs | RS2; }))); diff --git a/riscv/insns/amoswap_b.h b/riscv/insns/amoswap_b.h new file mode 100644 index 0000000..5ecbd26 --- /dev/null +++ b/riscv/insns/amoswap_b.h @@ -0,0 +1,3 @@ +require_extension('A'); +require_extension(EXT_ZABHA); +WRITE_RD((sreg_t)(int8_t)(MMU.amo(RS1, [&](uint8_t UNUSED lhs) { return RS2; }))); diff --git a/riscv/insns/amoxor_b.h b/riscv/insns/amoxor_b.h new file mode 100644 index 0000000..1966bd4 --- /dev/null +++ b/riscv/insns/amoxor_b.h @@ -0,0 +1,3 @@ +require_extension('A'); +require_extension(EXT_ZABHA); +WRITE_RD((sreg_t)(int8_t)(MMU.amo(RS1, [&](uint8_t lhs) { return lhs ^ RS2; }))); -- cgit v1.1 From 8dda7a208d290fd8e035aabd5ae6d42ff0e39a8f Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Mon, 30 Oct 2023 17:21:54 -0500 Subject: add halfword width amo instructions --- riscv/insns/amoadd_b.h | 3 +-- riscv/insns/amoadd_h.h | 2 ++ riscv/insns/amoand_b.h | 3 +-- riscv/insns/amoand_h.h | 2 ++ riscv/insns/amocas_b.h | 3 +-- riscv/insns/amocas_h.h | 3 +++ riscv/insns/amomax_b.h | 3 +-- riscv/insns/amomax_h.h | 2 ++ riscv/insns/amomaxu_b.h | 3 +-- riscv/insns/amomaxu_h.h | 2 ++ riscv/insns/amomin_b.h | 3 +-- riscv/insns/amomin_h.h | 2 ++ riscv/insns/amominu_b.h | 3 +-- riscv/insns/amominu_h.h | 2 ++ riscv/insns/amoor_b.h | 3 +-- riscv/insns/amoor_h.h | 2 ++ riscv/insns/amoswap_b.h | 3 +-- riscv/insns/amoswap_h.h | 2 ++ riscv/insns/amoxor_b.h | 3 +-- riscv/insns/amoxor_h.h | 2 ++ 20 files changed, 31 insertions(+), 20 deletions(-) create mode 100644 riscv/insns/amoadd_h.h create mode 100644 riscv/insns/amoand_h.h create mode 100644 riscv/insns/amocas_h.h create mode 100644 riscv/insns/amomax_h.h create mode 100644 riscv/insns/amomaxu_h.h create mode 100644 riscv/insns/amomin_h.h create mode 100644 riscv/insns/amominu_h.h create mode 100644 riscv/insns/amoor_h.h create mode 100644 riscv/insns/amoswap_h.h create mode 100644 riscv/insns/amoxor_h.h diff --git a/riscv/insns/amoadd_b.h b/riscv/insns/amoadd_b.h index 2138104..ce67488 100644 --- a/riscv/insns/amoadd_b.h +++ b/riscv/insns/amoadd_b.h @@ -1,3 +1,2 @@ -require_extension('A'); require_extension(EXT_ZABHA); -WRITE_RD((sreg_t)(int8_t)(MMU.amo(RS1, [&](uint8_t lhs) { return lhs + RS2; }))); +WRITE_RD(sreg_t(MMU.amo(RS1, [&](int8_t lhs) { return lhs + RS2; }))); diff --git a/riscv/insns/amoadd_h.h b/riscv/insns/amoadd_h.h new file mode 100644 index 0000000..93d2209 --- /dev/null +++ b/riscv/insns/amoadd_h.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZABHA); +WRITE_RD(sreg_t(MMU.amo(RS1, [&](int16_t lhs) { return lhs + RS2; }))); diff --git a/riscv/insns/amoand_b.h b/riscv/insns/amoand_b.h index f461c29..f103888 100644 --- a/riscv/insns/amoand_b.h +++ b/riscv/insns/amoand_b.h @@ -1,3 +1,2 @@ -require_extension('A'); require_extension(EXT_ZABHA); -WRITE_RD((sreg_t)(int8_t)(MMU.amo(RS1, [&](uint8_t lhs) { return lhs & RS2; }))); +WRITE_RD(sreg_t(MMU.amo(RS1, [&](int8_t lhs) { return lhs & RS2; }))); diff --git a/riscv/insns/amoand_h.h b/riscv/insns/amoand_h.h new file mode 100644 index 0000000..7034118 --- /dev/null +++ b/riscv/insns/amoand_h.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZABHA); +WRITE_RD(sreg_t(MMU.amo(RS1, [&](int16_t lhs) { return lhs & RS2; }))); diff --git a/riscv/insns/amocas_b.h b/riscv/insns/amocas_b.h index ca609c7..54ba824 100644 --- a/riscv/insns/amocas_b.h +++ b/riscv/insns/amocas_b.h @@ -1,4 +1,3 @@ -require_extension('A'); require_extension(EXT_ZACAS); require_extension(EXT_ZABHA); -WRITE_RD((sreg_t)(int8_t)(MMU.amo_compare_and_swap(RS1, RD, RS2))); +WRITE_RD(sreg_t(MMU.amo_compare_and_swap(RS1, RD, RS2))); diff --git a/riscv/insns/amocas_h.h b/riscv/insns/amocas_h.h new file mode 100644 index 0000000..064d041 --- /dev/null +++ b/riscv/insns/amocas_h.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZACAS); +require_extension(EXT_ZABHA); +WRITE_RD(sreg_t(MMU.amo_compare_and_swap(RS1, RD, RS2))); diff --git a/riscv/insns/amomax_b.h b/riscv/insns/amomax_b.h index 8187a3c..84df51a 100644 --- a/riscv/insns/amomax_b.h +++ b/riscv/insns/amomax_b.h @@ -1,3 +1,2 @@ -require_extension('A'); require_extension(EXT_ZABHA); -WRITE_RD((sreg_t)(int8_t)(MMU.amo(RS1, [&](int8_t lhs) { return std::max(lhs, int8_t(RS2)); }))); +WRITE_RD(sreg_t(MMU.amo(RS1, [&](int8_t lhs) { return std::max(lhs, int8_t(RS2)); }))); diff --git a/riscv/insns/amomax_h.h b/riscv/insns/amomax_h.h new file mode 100644 index 0000000..d91fe19 --- /dev/null +++ b/riscv/insns/amomax_h.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZABHA); +WRITE_RD(sreg_t(MMU.amo(RS1, [&](int16_t lhs) { return std::max(lhs, int16_t(RS2)); }))); diff --git a/riscv/insns/amomaxu_b.h b/riscv/insns/amomaxu_b.h index 534b3ca..d56b98e 100644 --- a/riscv/insns/amomaxu_b.h +++ b/riscv/insns/amomaxu_b.h @@ -1,3 +1,2 @@ -require_extension('A'); require_extension(EXT_ZABHA); -WRITE_RD((sreg_t)(int8_t)(MMU.amo(RS1, [&](uint8_t lhs) { return std::max(lhs, uint8_t(RS2)); }))); +WRITE_RD(sreg_t(MMU.amo(RS1, [&](uint8_t lhs) { return std::max(lhs, uint8_t(RS2)); }))); diff --git a/riscv/insns/amomaxu_h.h b/riscv/insns/amomaxu_h.h new file mode 100644 index 0000000..76cfa77 --- /dev/null +++ b/riscv/insns/amomaxu_h.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZABHA); +WRITE_RD(sreg_t(MMU.amo(RS1, [&](uint16_t lhs) { return std::max(lhs, uint16_t(RS2)); }))); diff --git a/riscv/insns/amomin_b.h b/riscv/insns/amomin_b.h index c5e8cf9..9b781e4 100644 --- a/riscv/insns/amomin_b.h +++ b/riscv/insns/amomin_b.h @@ -1,3 +1,2 @@ -require_extension('A'); require_extension(EXT_ZABHA); -WRITE_RD((sreg_t)(int8_t)(MMU.amo(RS1, [&](int8_t lhs) { return std::min(lhs, int8_t(RS2)); }))); +WRITE_RD(sreg_t(MMU.amo(RS1, [&](int8_t lhs) { return std::min(lhs, int8_t(RS2)); }))); diff --git a/riscv/insns/amomin_h.h b/riscv/insns/amomin_h.h new file mode 100644 index 0000000..4405ac3 --- /dev/null +++ b/riscv/insns/amomin_h.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZABHA); +WRITE_RD(sreg_t(MMU.amo(RS1, [&](int16_t lhs) { return std::min(lhs, int16_t(RS2)); }))); diff --git a/riscv/insns/amominu_b.h b/riscv/insns/amominu_b.h index 9bce0e7..7e12bf3 100644 --- a/riscv/insns/amominu_b.h +++ b/riscv/insns/amominu_b.h @@ -1,3 +1,2 @@ -require_extension('A'); require_extension(EXT_ZABHA); -WRITE_RD((sreg_t)(int8_t)(MMU.amo(RS1, [&](uint8_t lhs) { return std::min(lhs, uint8_t(RS2)); }))); +WRITE_RD(sreg_t(MMU.amo(RS1, [&](uint8_t lhs) { return std::min(lhs, uint8_t(RS2)); }))); diff --git a/riscv/insns/amominu_h.h b/riscv/insns/amominu_h.h new file mode 100644 index 0000000..60226fb --- /dev/null +++ b/riscv/insns/amominu_h.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZABHA); +WRITE_RD(sreg_t(MMU.amo(RS1, [&](uint16_t lhs) { return std::min(lhs, uint16_t(RS2)); }))); diff --git a/riscv/insns/amoor_b.h b/riscv/insns/amoor_b.h index f96ff54..3048ee9 100644 --- a/riscv/insns/amoor_b.h +++ b/riscv/insns/amoor_b.h @@ -1,3 +1,2 @@ -require_extension('A'); require_extension(EXT_ZABHA); -WRITE_RD((sreg_t)(int8_t)(MMU.amo(RS1, [&](uint8_t lhs) { return lhs | RS2; }))); +WRITE_RD(sreg_t(MMU.amo(RS1, [&](int8_t lhs) { return lhs | RS2; }))); diff --git a/riscv/insns/amoor_h.h b/riscv/insns/amoor_h.h new file mode 100644 index 0000000..1e71a51 --- /dev/null +++ b/riscv/insns/amoor_h.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZABHA); +WRITE_RD(sreg_t(MMU.amo(RS1, [&](int16_t lhs) { return lhs | RS2; }))); diff --git a/riscv/insns/amoswap_b.h b/riscv/insns/amoswap_b.h index 5ecbd26..54c9e6e 100644 --- a/riscv/insns/amoswap_b.h +++ b/riscv/insns/amoswap_b.h @@ -1,3 +1,2 @@ -require_extension('A'); require_extension(EXT_ZABHA); -WRITE_RD((sreg_t)(int8_t)(MMU.amo(RS1, [&](uint8_t UNUSED lhs) { return RS2; }))); +WRITE_RD(sreg_t(MMU.amo(RS1, [&](int8_t UNUSED lhs) { return RS2; }))); diff --git a/riscv/insns/amoswap_h.h b/riscv/insns/amoswap_h.h new file mode 100644 index 0000000..0c1a8ff --- /dev/null +++ b/riscv/insns/amoswap_h.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZABHA); +WRITE_RD(sreg_t(MMU.amo(RS1, [&](int16_t UNUSED lhs) { return RS2; }))); diff --git a/riscv/insns/amoxor_b.h b/riscv/insns/amoxor_b.h index 1966bd4..dbaf591 100644 --- a/riscv/insns/amoxor_b.h +++ b/riscv/insns/amoxor_b.h @@ -1,3 +1,2 @@ -require_extension('A'); require_extension(EXT_ZABHA); -WRITE_RD((sreg_t)(int8_t)(MMU.amo(RS1, [&](uint8_t lhs) { return lhs ^ RS2; }))); +WRITE_RD(sreg_t(MMU.amo(RS1, [&](int8_t lhs) { return lhs ^ RS2; }))); diff --git a/riscv/insns/amoxor_h.h b/riscv/insns/amoxor_h.h new file mode 100644 index 0000000..110acf7 --- /dev/null +++ b/riscv/insns/amoxor_h.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZABHA); +WRITE_RD(sreg_t(MMU.amo(RS1, [&](int16_t lhs) { return lhs ^ RS2; }))); -- cgit v1.1 From b96bf5565470a84b55976d50f07c5a42df633896 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Mon, 30 Oct 2023 17:22:32 -0500 Subject: Add encodings for Zabha instructions --- riscv/encoding.h | 62 +++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 61 insertions(+), 1 deletion(-) diff --git a/riscv/encoding.h b/riscv/encoding.h index 7ee3e3d..81d829c 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -4,7 +4,7 @@ /* * This file is auto-generated by running 'make' in - * https://github.com/riscv/riscv-opcodes (65c40e9) + * https://github.com/riscv/riscv-opcodes (37413c8) */ #ifndef RISCV_CSR_ENCODING_H @@ -426,46 +426,86 @@ #define MASK_AES64KS1I 0xff00707f #define MATCH_AES64KS2 0x7e000033 #define MASK_AES64KS2 0xfe00707f +#define MATCH_AMOADD_B 0x2f +#define MASK_AMOADD_B 0xf800707f #define MATCH_AMOADD_D 0x302f #define MASK_AMOADD_D 0xf800707f +#define MATCH_AMOADD_H 0x102f +#define MASK_AMOADD_H 0xf800707f #define MATCH_AMOADD_W 0x202f #define MASK_AMOADD_W 0xf800707f +#define MATCH_AMOAND_B 0x6000002f +#define MASK_AMOAND_B 0xf800707f #define MATCH_AMOAND_D 0x6000302f #define MASK_AMOAND_D 0xf800707f +#define MATCH_AMOAND_H 0x6000102f +#define MASK_AMOAND_H 0xf800707f #define MATCH_AMOAND_W 0x6000202f #define MASK_AMOAND_W 0xf800707f +#define MATCH_AMOCAS_B 0x2800002f +#define MASK_AMOCAS_B 0xf800707f #define MATCH_AMOCAS_D 0x2800302f #define MASK_AMOCAS_D 0xf800707f +#define MATCH_AMOCAS_H 0x2800102f +#define MASK_AMOCAS_H 0xf800707f #define MATCH_AMOCAS_Q 0x2800402f #define MASK_AMOCAS_Q 0xf800707f #define MATCH_AMOCAS_W 0x2800202f #define MASK_AMOCAS_W 0xf800707f +#define MATCH_AMOMAX_B 0xa000002f +#define MASK_AMOMAX_B 0xf800707f #define MATCH_AMOMAX_D 0xa000302f #define MASK_AMOMAX_D 0xf800707f +#define MATCH_AMOMAX_H 0xa000102f +#define MASK_AMOMAX_H 0xf800707f #define MATCH_AMOMAX_W 0xa000202f #define MASK_AMOMAX_W 0xf800707f +#define MATCH_AMOMAXU_B 0xe000002f +#define MASK_AMOMAXU_B 0xf800707f #define MATCH_AMOMAXU_D 0xe000302f #define MASK_AMOMAXU_D 0xf800707f +#define MATCH_AMOMAXU_H 0xe000102f +#define MASK_AMOMAXU_H 0xf800707f #define MATCH_AMOMAXU_W 0xe000202f #define MASK_AMOMAXU_W 0xf800707f +#define MATCH_AMOMIN_B 0x8000002f +#define MASK_AMOMIN_B 0xf800707f #define MATCH_AMOMIN_D 0x8000302f #define MASK_AMOMIN_D 0xf800707f +#define MATCH_AMOMIN_H 0x8000102f +#define MASK_AMOMIN_H 0xf800707f #define MATCH_AMOMIN_W 0x8000202f #define MASK_AMOMIN_W 0xf800707f +#define MATCH_AMOMINU_B 0xc000002f +#define MASK_AMOMINU_B 0xf800707f #define MATCH_AMOMINU_D 0xc000302f #define MASK_AMOMINU_D 0xf800707f +#define MATCH_AMOMINU_H 0xc000102f +#define MASK_AMOMINU_H 0xf800707f #define MATCH_AMOMINU_W 0xc000202f #define MASK_AMOMINU_W 0xf800707f +#define MATCH_AMOOR_B 0x4000002f +#define MASK_AMOOR_B 0xf800707f #define MATCH_AMOOR_D 0x4000302f #define MASK_AMOOR_D 0xf800707f +#define MATCH_AMOOR_H 0x4000102f +#define MASK_AMOOR_H 0xf800707f #define MATCH_AMOOR_W 0x4000202f #define MASK_AMOOR_W 0xf800707f +#define MATCH_AMOSWAP_B 0x800002f +#define MASK_AMOSWAP_B 0xf800707f #define MATCH_AMOSWAP_D 0x800302f #define MASK_AMOSWAP_D 0xf800707f +#define MATCH_AMOSWAP_H 0x800102f +#define MASK_AMOSWAP_H 0xf800707f #define MATCH_AMOSWAP_W 0x800202f #define MASK_AMOSWAP_W 0xf800707f +#define MATCH_AMOXOR_B 0x2000002f +#define MASK_AMOXOR_B 0xf800707f #define MATCH_AMOXOR_D 0x2000302f #define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOXOR_H 0x2000102f +#define MASK_AMOXOR_H 0xf800707f #define MATCH_AMOXOR_W 0x2000202f #define MASK_AMOXOR_W 0xf800707f #define MATCH_AND 0x7033 @@ -3655,26 +3695,46 @@ DECLARE_INSN(aes64esm, MATCH_AES64ESM, MASK_AES64ESM) DECLARE_INSN(aes64im, MATCH_AES64IM, MASK_AES64IM) DECLARE_INSN(aes64ks1i, MATCH_AES64KS1I, MASK_AES64KS1I) DECLARE_INSN(aes64ks2, MATCH_AES64KS2, MASK_AES64KS2) +DECLARE_INSN(amoadd_b, MATCH_AMOADD_B, MASK_AMOADD_B) DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoadd_h, MATCH_AMOADD_H, MASK_AMOADD_H) DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoand_b, MATCH_AMOAND_B, MASK_AMOAND_B) DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amoand_h, MATCH_AMOAND_H, MASK_AMOAND_H) DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amocas_b, MATCH_AMOCAS_B, MASK_AMOCAS_B) DECLARE_INSN(amocas_d, MATCH_AMOCAS_D, MASK_AMOCAS_D) +DECLARE_INSN(amocas_h, MATCH_AMOCAS_H, MASK_AMOCAS_H) DECLARE_INSN(amocas_q, MATCH_AMOCAS_Q, MASK_AMOCAS_Q) DECLARE_INSN(amocas_w, MATCH_AMOCAS_W, MASK_AMOCAS_W) +DECLARE_INSN(amomax_b, MATCH_AMOMAX_B, MASK_AMOMAX_B) DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amomax_h, MATCH_AMOMAX_H, MASK_AMOMAX_H) DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amomaxu_b, MATCH_AMOMAXU_B, MASK_AMOMAXU_B) DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amomaxu_h, MATCH_AMOMAXU_H, MASK_AMOMAXU_H) DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amomin_b, MATCH_AMOMIN_B, MASK_AMOMIN_B) DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomin_h, MATCH_AMOMIN_H, MASK_AMOMIN_H) DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amominu_b, MATCH_AMOMINU_B, MASK_AMOMINU_B) DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amominu_h, MATCH_AMOMINU_H, MASK_AMOMINU_H) DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amoor_b, MATCH_AMOOR_B, MASK_AMOOR_B) DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoor_h, MATCH_AMOOR_H, MASK_AMOOR_H) DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoswap_b, MATCH_AMOSWAP_B, MASK_AMOSWAP_B) DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(amoswap_h, MATCH_AMOSWAP_H, MASK_AMOSWAP_H) DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(amoxor_b, MATCH_AMOXOR_B, MASK_AMOXOR_B) DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoxor_h, MATCH_AMOXOR_H, MASK_AMOXOR_H) DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) DECLARE_INSN(and, MATCH_AND, MASK_AND) DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) -- cgit v1.1 From 2adfab25a5c206afdd7c06855cbe2e27536d633e Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Mon, 30 Oct 2023 17:23:22 -0500 Subject: Add enum for Zabha extension --- riscv/isa_parser.h | 1 + 1 file changed, 1 insertion(+) diff --git a/riscv/isa_parser.h b/riscv/isa_parser.h index fac4186..a84b6fe 100644 --- a/riscv/isa_parser.h +++ b/riscv/isa_parser.h @@ -76,6 +76,7 @@ typedef enum { EXT_XZBT, EXT_SSTC, EXT_ZACAS, + EXT_ZABHA, EXT_INTERNAL_ZFH_MOVE, EXT_SMCSRIND, EXT_SSCSRIND, -- cgit v1.1 From 04cbaf0c1c609506b8fc74e756305e0d792fa784 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Mon, 30 Oct 2023 17:24:43 -0500 Subject: Add Zabha instructions to disasm --- disasm/disasm.cc | 23 +++++++++++++++++++++++ disasm/isa_parser.cc | 6 ++++++ 2 files changed, 29 insertions(+) diff --git a/disasm/disasm.cc b/disasm/disasm.cc index df02e03..6917fa5 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -840,6 +840,29 @@ void disassembler_t::add_instructions(const isa_parser_t* isa) DEFINE_XAMO(amocas_q) } + if (isa->extension_enabled(EXT_ZABHA)) { + DEFINE_XAMO(amoadd_b) + DEFINE_XAMO(amoswap_b) + DEFINE_XAMO(amoand_b) + DEFINE_XAMO(amoor_b) + DEFINE_XAMO(amoxor_b) + DEFINE_XAMO(amomin_b) + DEFINE_XAMO(amomax_b) + DEFINE_XAMO(amominu_b) + DEFINE_XAMO(amomaxu_b) + DEFINE_XAMO(amocas_b) + DEFINE_XAMO(amoadd_h) + DEFINE_XAMO(amoswap_h) + DEFINE_XAMO(amoand_h) + DEFINE_XAMO(amoor_h) + DEFINE_XAMO(amoxor_h) + DEFINE_XAMO(amomin_h) + DEFINE_XAMO(amomax_h) + DEFINE_XAMO(amominu_h) + DEFINE_XAMO(amomaxu_h) + DEFINE_XAMO(amocas_h) + } + add_insn(new disasm_insn_t("j", match_jal, mask_jal | mask_rd, {&jump_target})); add_insn(new disasm_insn_t("jal", match_jal | match_rd_ra, mask_jal | mask_rd, {&jump_target})); add_insn(new disasm_insn_t("jal", match_jal, mask_jal, {&xrd, &jump_target})); diff --git a/disasm/isa_parser.cc b/disasm/isa_parser.cc index 563f687..ef51310 100644 --- a/disasm/isa_parser.cc +++ b/disasm/isa_parser.cc @@ -121,6 +121,8 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv) // HINTs encoded in base-ISA instructions are always present. } else if (ext_str == "zacas") { extension_table[EXT_ZACAS] = true; + } else if (ext_str == "zabha") { + extension_table[EXT_ZABHA] = true; } else if (ext_str == "zmmul") { extension_table[EXT_ZMMUL] = true; } else if (ext_str == "zba") { @@ -357,6 +359,10 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv) bad_isa_string(str, "'Zacas' extension requires 'A' extension"); } + if (extension_table[EXT_ZABHA] && !extension_table['A']) { + bad_isa_string(str, "'Zabha' extension requires 'A' extension"); + } + // Zpn conflicts with Zvknha/Zvknhb in both rv32 and rv64 if (extension_table[EXT_ZPN] && (extension_table[EXT_ZVKNHA] || extension_table[EXT_ZVKNHB])) { bad_isa_string(str, "'Zvkna' and 'Zvknhb' extensions are incompatible with 'Zpn' extension"); -- cgit v1.1 From 5a984591563bb3bbb54ccf0e82a2b732b650da75 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Mon, 30 Oct 2023 17:25:06 -0500 Subject: Add Zabha instructions to make --- riscv/riscv.mk.in | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index f0c55aa..76c2ed7 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -1300,6 +1300,28 @@ riscv_insn_ext_zacas = \ amocas_d \ $(if $(HAVE_INT128),amocas_q) +riscv_insn_ext_zabha = \ + amoadd_b \ + amoand_b \ + amomax_b \ + amomaxu_b \ + amomin_b \ + amominu_b \ + amoor_b \ + amoswap_b \ + amoxor_b \ + amocas_b \ + amoadd_h \ + amoand_h \ + amomax_h \ + amomaxu_h \ + amomin_h \ + amominu_h \ + amoor_h \ + amoswap_h \ + amoxor_h \ + amocas_h \ + riscv_insn_ext_zalasr = \ lb_aq \ lh_aq \ @@ -1394,6 +1416,7 @@ riscv_insn_list = \ $(riscv_insn_ext_q) \ $(riscv_insn_ext_q_zfa) \ $(riscv_insn_ext_zacas) \ + $(riscv_insn_ext_zabha) \ $(riscv_insn_ext_zalasr) \ $(riscv_insn_ext_zce) \ $(riscv_insn_ext_zfh) \ -- cgit v1.1