From 4061ee6e184dab1e39c7448c248aa8f74b3f150b Mon Sep 17 00:00:00 2001 From: Udit Khanna Date: Tue, 12 May 2020 00:37:50 -0700 Subject: Hardwire mstatus.[sie,spie] to zero if 'S' mode absent --- riscv/processor.cc | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/riscv/processor.cc b/riscv/processor.cc index b5ee590..0edf193 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -742,9 +742,8 @@ void processor_t::set_csr(int which, reg_t val) || supports_extension('V'); bool has_vs = supports_extension('V'); - reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE - | MSTATUS_MPRV - | (supports_extension('S') ? MSTATUS_SUM : 0) + reg_t mask = MSTATUS_MIE | MSTATUS_MPIE | MSTATUS_MPRV + | (supports_extension('S') ? (MSTATUS_SUM | MSTATUS_SIE | MSTATUS_SPIE) : 0) | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM | MSTATUS_TSR | (has_fs ? MSTATUS_FS : 0) | (has_vs ? MSTATUS_VS : 0) -- cgit v1.1