From 3fc52f5989e498aeaad147b5b5591d63e27ca9a9 Mon Sep 17 00:00:00 2001 From: Chih-Min Chao Date: Mon, 16 Sep 2019 01:17:09 -0700 Subject: rvv: fix vmv.x.s signed-ext issue Signed-off-by: Chih-Min Chao --- riscv/insns/vmv_x_s.h | 47 +++++++++++++++++++++++++---------------------- riscv/riscv.mk.in | 2 +- 2 files changed, 26 insertions(+), 23 deletions(-) diff --git a/riscv/insns/vmv_x_s.h b/riscv/insns/vmv_x_s.h index f22c2dd..50f2e79 100644 --- a/riscv/insns/vmv_x_s.h +++ b/riscv/insns/vmv_x_s.h @@ -1,25 +1,28 @@ -// vext_x_v: rd = vs2[0] +// vmv_x_s: rd = vs2[rs1] require(insn.v_vm() == 1); uint64_t xmask = UINT64_MAX >> (64 - P.get_max_xlen()); -VI_LOOP_BASE -VI_LOOP_END_NO_TAIL_ZERO -switch(sew) { -case e8: - WRITE_RD(P.VU.elt(rs2_num, 0)); - break; -case e16: - WRITE_RD(P.VU.elt(rs2_num, 0)); - break; -case e32: - if (P.get_max_xlen() == 32) - WRITE_RD(P.VU.elt(rs2_num, 0)); - else - WRITE_RD(P.VU.elt(rs2_num, 0)); - break; -case e64: - if (P.get_max_xlen() <= sew) - WRITE_RD(P.VU.elt(rs2_num, 0) & xmask); - else - WRITE_RD(P.VU.elt(rs2_num, 0)); - break; +reg_t rs1 = RS1; +reg_t sew = P.VU.vsew; +reg_t rs2_num = insn.rs2(); + +if (!(rs1 >= 0 && rs1 < (P.VU.get_vlen() / sew))) { + WRITE_RD(0); +} else { + switch(sew) { + case e8: + WRITE_RD(P.VU.elt(rs2_num, rs1)); + break; + case e16: + WRITE_RD(P.VU.elt(rs2_num, rs1)); + break; + case e32: + WRITE_RD(P.VU.elt(rs2_num, rs1)); + break; + case e64: + if (P.get_max_xlen() <= sew) + WRITE_RD(P.VU.elt(rs2_num, rs1) & xmask); + else + WRITE_RD(P.VU.elt(rs2_num, rs1)); + break; + } } diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 50775e1..15ca3b9 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -315,7 +315,6 @@ riscv_insn_ext_v_alu_int = \ vdivu_vx \ vdot_vv \ vdotu_vv \ - vmv_x_s \ vid_v \ viota_m \ vmacc_vv \ @@ -381,6 +380,7 @@ riscv_insn_ext_v_alu_int = \ vmv_v_i \ vmv_v_v \ vmv_v_x \ + vmv_x_s \ vmxnor_mm \ vmxor_mm \ vnclip_vi \ -- cgit v1.1