From 3f7c06a2b25ebf033d2ad233c1ccde1f833b2e55 Mon Sep 17 00:00:00 2001 From: Chih-Min Chao Date: Tue, 21 Apr 2020 20:35:32 -0700 Subject: rvv: fix floating comparison for fp16 Signed-off-by: Chih-Min Chao --- riscv/decode.h | 33 ++++++++++++++++++++++----------- riscv/insns/vfwadd_vf.h | 3 +++ riscv/insns/vfwadd_wf.h | 3 +++ riscv/insns/vfwmacc_vf.h | 3 +++ riscv/insns/vfwmsac_vf.h | 3 +++ riscv/insns/vfwmul_vf.h | 3 +++ riscv/insns/vfwnmacc_vf.h | 3 +++ riscv/insns/vfwnmsac_vf.h | 3 +++ riscv/insns/vfwsub_vf.h | 3 +++ riscv/insns/vfwsub_wf.h | 3 +++ 10 files changed, 49 insertions(+), 11 deletions(-) diff --git a/riscv/decode.h b/riscv/decode.h index 2d923b1..f9c3bc8 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -1689,19 +1689,18 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \ #define VI_VFP_LOOP_CMP_END \ switch(P.VU.vsew) { \ + case e16: \ case e32: \ case e64: { \ vdi = (vdi & ~mmask) | (((res) << mpos) & mmask); \ break; \ } \ - case e16: \ default: \ require(0); \ break; \ }; \ } \ - P.VU.vstart = 0; \ - set_fp_exceptions; + P.VU.vstart = 0; #define VI_VFP_VV_LOOP(BODY16, BODY32, BODY64) \ VI_CHECK_SSS(true); \ @@ -1927,20 +1926,26 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \ }; \ VI_VFP_LOOP_CMP_END \ -#define VI_VFP_VF_LOOP_WIDE(BODY) \ +#define VI_VFP_VF_LOOP_WIDE(BODY16, BODY32) \ VI_CHECK_DSS(false); \ VI_VFP_LOOP_BASE \ switch(P.VU.vsew) { \ + case e16: { \ + float32_t &vd = P.VU.elt(rd_num, i, true); \ + float32_t vs2 = f16_to_f32(P.VU.elt(rs2_num, i)); \ + float32_t rs1 = f16_to_f32(f16(READ_FREG(rs1_num))); \ + BODY16; \ + set_fp_exceptions; \ + break; \ + } \ case e32: {\ float64_t &vd = P.VU.elt(rd_num, i, true); \ float64_t vs2 = f32_to_f64(P.VU.elt(rs2_num, i)); \ float64_t rs1 = f32_to_f64(f32(READ_FREG(rs1_num))); \ - BODY; \ + BODY32; \ set_fp_exceptions; \ break; \ }\ - case e16: \ - case e8: \ default: \ require(0); \ break; \ @@ -1970,20 +1975,26 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \ DEBUG_RVV_FP_VV; \ VI_VFP_LOOP_END -#define VI_VFP_WF_LOOP_WIDE(BODY) \ +#define VI_VFP_WF_LOOP_WIDE(BODY16, BODY32) \ VI_CHECK_DDS(false); \ VI_VFP_LOOP_BASE \ switch(P.VU.vsew) { \ + case e16: {\ + float32_t &vd = P.VU.elt(rd_num, i, true); \ + float32_t vs2 = P.VU.elt(rs2_num, i); \ + float32_t rs1 = f16_to_f32(f16(READ_FREG(rs1_num))); \ + BODY16; \ + set_fp_exceptions; \ + break; \ + }\ case e32: {\ float64_t &vd = P.VU.elt(rd_num, i, true); \ float64_t vs2 = P.VU.elt(rs2_num, i); \ float64_t rs1 = f32_to_f64(f32(READ_FREG(rs1_num))); \ - BODY; \ + BODY32; \ set_fp_exceptions; \ break; \ }\ - case e16: \ - case e8: \ default: \ require(0); \ }; \ diff --git a/riscv/insns/vfwadd_vf.h b/riscv/insns/vfwadd_vf.h index ecac202..b824900 100644 --- a/riscv/insns/vfwadd_vf.h +++ b/riscv/insns/vfwadd_vf.h @@ -1,5 +1,8 @@ // vfwadd.vf vd, vs2, rs1 VI_VFP_VF_LOOP_WIDE ({ + vd = f32_add(vs2, rs1); +}, +{ vd = f64_add(vs2, rs1); }) diff --git a/riscv/insns/vfwadd_wf.h b/riscv/insns/vfwadd_wf.h index eb38d0d..021b17f 100644 --- a/riscv/insns/vfwadd_wf.h +++ b/riscv/insns/vfwadd_wf.h @@ -1,5 +1,8 @@ // vfwadd.wf vd, vs2, vs1 VI_VFP_WF_LOOP_WIDE ({ + vd = f32_add(vs2, rs1); +}, +{ vd = f64_add(vs2, rs1); }) diff --git a/riscv/insns/vfwmacc_vf.h b/riscv/insns/vfwmacc_vf.h index 6ee011e..441fa0a 100644 --- a/riscv/insns/vfwmacc_vf.h +++ b/riscv/insns/vfwmacc_vf.h @@ -1,5 +1,8 @@ // vfwmacc.vf vd, vs2, rs1 VI_VFP_VF_LOOP_WIDE ({ + vd = f32_mulAdd(rs1, vs2, vd); +}, +{ vd = f64_mulAdd(rs1, vs2, vd); }) diff --git a/riscv/insns/vfwmsac_vf.h b/riscv/insns/vfwmsac_vf.h index ea8f050..18010ff 100644 --- a/riscv/insns/vfwmsac_vf.h +++ b/riscv/insns/vfwmsac_vf.h @@ -1,5 +1,8 @@ // vfwmsac.vf vd, vs2, rs1 VI_VFP_VF_LOOP_WIDE ({ + vd = f32_mulAdd(rs1, vs2, f32(vd.v ^ F32_SIGN)); +}, +{ vd = f64_mulAdd(rs1, vs2, f64(vd.v ^ F64_SIGN)); }) diff --git a/riscv/insns/vfwmul_vf.h b/riscv/insns/vfwmul_vf.h index 884e66f..2bb543f 100644 --- a/riscv/insns/vfwmul_vf.h +++ b/riscv/insns/vfwmul_vf.h @@ -1,5 +1,8 @@ // vfwmul.vf vd, vs2, rs1 VI_VFP_VF_LOOP_WIDE ({ + vd = f32_mul(vs2, rs1); +}, +{ vd = f64_mul(vs2, rs1); }) diff --git a/riscv/insns/vfwnmacc_vf.h b/riscv/insns/vfwnmacc_vf.h index bccc24f..038bda0 100644 --- a/riscv/insns/vfwnmacc_vf.h +++ b/riscv/insns/vfwnmacc_vf.h @@ -1,5 +1,8 @@ // vfwnmacc.vf vd, vs2, rs1 VI_VFP_VF_LOOP_WIDE ({ + vd = f32_mulAdd(f32(rs1.v ^ F32_SIGN), vs2, f32(vd.v ^ F32_SIGN)); +}, +{ vd = f64_mulAdd(f64(rs1.v ^ F64_SIGN), vs2, f64(vd.v ^ F64_SIGN)); }) diff --git a/riscv/insns/vfwnmsac_vf.h b/riscv/insns/vfwnmsac_vf.h index 32ef624..1e288e1 100644 --- a/riscv/insns/vfwnmsac_vf.h +++ b/riscv/insns/vfwnmsac_vf.h @@ -1,5 +1,8 @@ // vfwnmacc.vf vd, vs2, rs1 VI_VFP_VF_LOOP_WIDE ({ + vd = f32_mulAdd(f32(rs1.v ^ F32_SIGN), vs2, vd); +}, +{ vd = f64_mulAdd(f64(rs1.v ^ F64_SIGN), vs2, vd); }) diff --git a/riscv/insns/vfwsub_vf.h b/riscv/insns/vfwsub_vf.h index 1d20c38..8c37688 100644 --- a/riscv/insns/vfwsub_vf.h +++ b/riscv/insns/vfwsub_vf.h @@ -1,5 +1,8 @@ // vfwsub.vf vd, vs2, rs1 VI_VFP_VF_LOOP_WIDE ({ + vd = f32_sub(vs2, rs1); +}, +{ vd = f64_sub(vs2, rs1); }) diff --git a/riscv/insns/vfwsub_wf.h b/riscv/insns/vfwsub_wf.h index fa3d747..f6f47ca 100644 --- a/riscv/insns/vfwsub_wf.h +++ b/riscv/insns/vfwsub_wf.h @@ -1,5 +1,8 @@ // vfwsub.wf vd, vs2, rs1 VI_VFP_WF_LOOP_WIDE ({ + vd = f32_sub(vs2, rs1); +}, +{ vd = f64_sub(vs2, rs1); }) -- cgit v1.1