From 316ae3888dae19bbb27d4dbd719d1bc0fb39a9e0 Mon Sep 17 00:00:00 2001 From: Chih-Min Chao Date: Thu, 21 May 2020 21:29:43 -0700 Subject: rvv: remove remove vlmul Signed-off-by: Chih-Min Chao --- riscv/execute.cc | 10 ++++++---- riscv/insns/vcompress_vm.h | 6 +++--- riscv/insns/vfmv_v_f.h | 2 +- riscv/insns/vid_v.h | 5 ++--- riscv/insns/viota_m.h | 7 +++---- riscv/insns/vrgather_vi.h | 7 +++---- riscv/insns/vrgather_vv.h | 9 ++++----- riscv/insns/vrgather_vx.h | 7 +++---- riscv/processor.cc | 5 +++-- riscv/processor.h | 2 +- 10 files changed, 29 insertions(+), 31 deletions(-) diff --git a/riscv/execute.cc b/riscv/execute.cc index 5cd29b7..2ed7546 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -107,7 +107,10 @@ static void commit_log_print_insn(processor_t *p, reg_t pc, insn_t insn) } if (!show_vec && (is_vreg || is_vec)) { - fprintf(log_file, " e%ld m%ld l%ld", p->VU.vsew, p->VU.vlmul, p->VU.vl); + if (p->VU.vflmul < 0) + fprintf(log_file, " e%ld mf%ld l%ld", p->VU.vsew, (reg_t)(1.0/p->VU.vflmul), p->VU.vl); + else + fprintf(log_file, " e%ld m%ld l%ld", p->VU.vsew, (reg_t)p->VU.vflmul, p->VU.vl); show_vec = true; } @@ -253,10 +256,9 @@ void processor_t::step(size_t n) #if 1 if (debug && !state.serialized) { prev_reg_state_t *saved = prev_state; - float vlmul = VU.fractional_lmul? VU.vflmul : VU.vlmul; if (saved->VU.setvl_count != VU.setvl_count) { fprintf(stderr, "vconfig <- sew=%lu vlmul=%.3f vlmax=%lu vl=%lu vta=%ld vma=%ld\n", - VU.vsew, vlmul, VU.vlmax, VU.vl, VU.vta, VU.vma); + VU.vsew, VU.vflmul, VU.vlmax, VU.vl, VU.vta, VU.vma); saved->VU.setvl_count = VU.setvl_count; } for (int i=0; iVU.elt(i, j); uint32_t now = VU.elt(i, j); diff --git a/riscv/insns/vcompress_vm.h b/riscv/insns/vcompress_vm.h index a2b810a..325e40a 100644 --- a/riscv/insns/vcompress_vm.h +++ b/riscv/insns/vcompress_vm.h @@ -1,9 +1,9 @@ // vcompress vd, vs2, vs1 require(P.VU.vstart == 0); -require((insn.rd() & (P.VU.vlmul - 1)) == 0); -require((insn.rs2() & (P.VU.vlmul - 1)) == 0); +require_align(insn.rd(), P.VU.vflmul); +require_align(insn.rs2(), P.VU.vflmul); require(insn.rd() != insn.rs2()); -require(!is_overlapped(insn.rd(), P.VU.vlmul, insn.rs1(), 1)); +require_noover(insn.rd(), P.VU.vflmul, insn.rs1(), 1); reg_t pos = 0; diff --git a/riscv/insns/vfmv_v_f.h b/riscv/insns/vfmv_v_f.h index e4cdec4..fb9c788 100644 --- a/riscv/insns/vfmv_v_f.h +++ b/riscv/insns/vfmv_v_f.h @@ -1,5 +1,5 @@ // vfmv_vf vd, vs1 -require((insn.rd() & (P.VU.vlmul - 1)) == 0); +require_align(insn.rd(), P.VU.vflmul); VI_VFP_COMMON switch(P.VU.vsew) { case e16: diff --git a/riscv/insns/vid_v.h b/riscv/insns/vid_v.h index dc9a2d1..786432f 100644 --- a/riscv/insns/vid_v.h +++ b/riscv/insns/vid_v.h @@ -6,9 +6,8 @@ reg_t sew = P.VU.vsew; reg_t rd_num = insn.rd(); reg_t rs1_num = insn.rs1(); reg_t rs2_num = insn.rs2(); -require((rd_num & (P.VU.vlmul - 1)) == 0); -if (insn.v_vm() == 0) \ - require(insn.rd() != 0); +require_align(rd_num, P.VU.vflmul); +require_vm; for (reg_t i = P.VU.vstart ; i < P.VU.vl; ++i) { VI_LOOP_ELEMENT_SKIP(); diff --git a/riscv/insns/viota_m.h b/riscv/insns/viota_m.h index 642a7f9..69c0d20 100644 --- a/riscv/insns/viota_m.h +++ b/riscv/insns/viota_m.h @@ -7,10 +7,9 @@ reg_t rd_num = insn.rd(); reg_t rs1_num = insn.rs1(); reg_t rs2_num = insn.rs2(); require(P.VU.vstart == 0); -require(!is_overlapped(rd_num, P.VU.vlmul, rs2_num, 1)); -if (insn.v_vm() == 0) - require(!is_overlapped(rd_num, P.VU.vlmul, 0, 1)); -require((rd_num & (P.VU.vlmul - 1)) == 0); +require_noover(rd_num, P.VU.vflmul, rs2_num, 1); +require_vm; +require_align(rd_num, P.VU.vflmul); int cnt = 0; for (reg_t i = 0; i < vl; ++i) { diff --git a/riscv/insns/vrgather_vi.h b/riscv/insns/vrgather_vi.h index f63110e..385e9be 100644 --- a/riscv/insns/vrgather_vi.h +++ b/riscv/insns/vrgather_vi.h @@ -1,9 +1,8 @@ // vrgather.vi vd, vs2, zimm5 vm # vd[i] = (zimm5 >= VLMAX) ? 0 : vs2[zimm5]; -require((insn.rd() & (P.VU.vlmul - 1)) == 0); -require((insn.rs2() & (P.VU.vlmul - 1)) == 0); +require_align(insn.rd(), P.VU.vflmul); +require_align(insn.rs2(), P.VU.vflmul); require(insn.rd() != insn.rs2()); -if (insn.v_vm() == 0) - require(insn.rd() != 0); +require_vm; reg_t zimm5 = insn.v_zimm5(); diff --git a/riscv/insns/vrgather_vv.h b/riscv/insns/vrgather_vv.h index 822e197..a3a32f5 100644 --- a/riscv/insns/vrgather_vv.h +++ b/riscv/insns/vrgather_vv.h @@ -1,10 +1,9 @@ // vrgather.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; -require((insn.rd() & (P.VU.vlmul - 1)) == 0); -require((insn.rs2() & (P.VU.vlmul - 1)) == 0); -require((insn.rs1() & (P.VU.vlmul - 1)) == 0); +require_align(insn.rd(), P.VU.vflmul); +require_align(insn.rs2(), P.VU.vflmul); +require_align(insn.rs1(), P.VU.vflmul); require(insn.rd() != insn.rs2() && insn.rd() != insn.rs1()); -if (insn.v_vm() == 0) - require(insn.rd() != 0); +require_vm; VI_LOOP_BASE switch (sew) { diff --git a/riscv/insns/vrgather_vx.h b/riscv/insns/vrgather_vx.h index a91d58c..058ffae 100644 --- a/riscv/insns/vrgather_vx.h +++ b/riscv/insns/vrgather_vx.h @@ -1,9 +1,8 @@ // vrgather.vx vd, vs2, rs1, vm # vd[i] = (rs1 >= VLMAX) ? 0 : vs2[rs1]; -require((insn.rd() & (P.VU.vlmul - 1)) == 0); -require((insn.rs2() & (P.VU.vlmul - 1)) == 0); +require_align(insn.rd(), P.VU.vflmul); +require_align(insn.rs2(), P.VU.vflmul); require(insn.rd() != insn.rs2()); -if (insn.v_vm() == 0) - require(insn.rd() != 0); +require_vm; reg_t rs1 = RS1; diff --git a/riscv/processor.cc b/riscv/processor.cc index 1dfd563..34ab01c 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -377,6 +377,7 @@ void processor_t::vectorUnit_t::reset(){ } reg_t processor_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t newType){ + reg_t vlmul = 0; if (vtype != newType){ vtype = newType; vsew = 1 << (BITS(newType, 4, 2) + 3); @@ -401,7 +402,7 @@ reg_t processor_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t newT break; } vlmax = (VLEN/vsew)/vlmul; - vflmul = 1/(float)vlmul; + vflmul = 1.0/vlmul; vlmul = 1; } else { vlmul = 1 << vlmul; @@ -409,7 +410,7 @@ reg_t processor_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t newT vflmul = vlmul; } - vill = !(vlmul>=1 && vlmul <=8) || vsew > ELEN || vediv != 1 || (newType >> 8) != 0; + vill = !(vflmul >= 0.125 && vflmul <= 8) || vsew > ELEN || vediv != 1 || (newType >> 8) != 0; if (vill) { vlmax = 0; vtype = UINT64_MAX << (p->get_xlen() - 1); diff --git a/riscv/processor.h b/riscv/processor.h index be1ffea..4164939 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -452,7 +452,7 @@ public: reg_t vlmax; reg_t vstart, vxrm, vxsat, vl, vtype, vlenb; reg_t vma, vta; - reg_t vediv, vsew, vlmul; + reg_t vediv, vsew; reg_t veew; float vemul; float vflmul; -- cgit v1.1