From 2c3ff5536d792f564c5c97aff691ccda6a0b9e84 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@s144.Millennium.Berkeley.EDU>
Date: Mon, 14 Feb 2011 23:44:13 -0800
Subject: [xcc,opcodes,pk,sim] krste's re-renaming spree

---
 riscv/execute.h         | 186 ++++++++++++++++++++++++------------------------
 riscv/insns/fc_eq_d.h   |   3 -
 riscv/insns/fc_eq_s.h   |   3 -
 riscv/insns/fc_le_d.h   |   3 -
 riscv/insns/fc_le_s.h   |   3 -
 riscv/insns/fc_lt_d.h   |   3 -
 riscv/insns/fc_lt_s.h   |   3 -
 riscv/insns/fcvt_d_lu.h |   5 ++
 riscv/insns/fcvt_d_wu.h |   4 ++
 riscv/insns/fcvt_lu_d.h |   5 ++
 riscv/insns/fcvt_lu_s.h |   5 ++
 riscv/insns/fcvt_s_lu.h |   5 ++
 riscv/insns/fcvt_s_wu.h |   4 ++
 riscv/insns/fcvt_wu_d.h |   4 ++
 riscv/insns/fcvt_wu_s.h |   4 ++
 riscv/insns/fcvtu_d_l.h |   5 --
 riscv/insns/fcvtu_d_w.h |   4 --
 riscv/insns/fcvtu_l_d.h |   5 --
 riscv/insns/fcvtu_l_s.h |   5 --
 riscv/insns/fcvtu_s_l.h |   5 --
 riscv/insns/fcvtu_s_w.h |   4 --
 riscv/insns/fcvtu_w_d.h |   4 --
 riscv/insns/fcvtu_w_s.h |   4 --
 riscv/insns/feq_d.h     |   3 +
 riscv/insns/feq_s.h     |   3 +
 riscv/insns/fld.h       |   2 +
 riscv/insns/fle_d.h     |   3 +
 riscv/insns/fle_s.h     |   3 +
 riscv/insns/flt_d.h     |   3 +
 riscv/insns/flt_s.h     |   3 +
 riscv/insns/flw.h       |   2 +
 riscv/insns/fsd.h       |   2 +
 riscv/insns/fsgnj_d.h   |   2 +
 riscv/insns/fsgnj_s.h   |   2 +
 riscv/insns/fsgnjn_d.h  |   2 +
 riscv/insns/fsgnjn_s.h  |   2 +
 riscv/insns/fsgnjx_d.h  |   2 +
 riscv/insns/fsgnjx_s.h  |   2 +
 riscv/insns/fsinj_d.h   |   2 -
 riscv/insns/fsinj_s.h   |   2 -
 riscv/insns/fsinjn_d.h  |   2 -
 riscv/insns/fsinjn_s.h  |   2 -
 riscv/insns/fsmul_d.h   |   2 -
 riscv/insns/fsmul_s.h   |   2 -
 riscv/insns/fsw.h       |   2 +
 riscv/insns/l_b.h       |   1 -
 riscv/insns/l_bu.h      |   1 -
 riscv/insns/l_d.h       |   2 -
 riscv/insns/l_h.h       |   1 -
 riscv/insns/l_hu.h      |   1 -
 riscv/insns/l_w.h       |   1 -
 riscv/insns/l_wu.h      |   1 -
 riscv/insns/lb.h        |   1 +
 riscv/insns/lbu.h       |   1 +
 riscv/insns/ld.h        |   2 +
 riscv/insns/lf_d.h      |   2 -
 riscv/insns/lf_w.h      |   2 -
 riscv/insns/lh.h        |   1 +
 riscv/insns/lhu.h       |   1 +
 riscv/insns/lw.h        |   1 +
 riscv/insns/lwu.h       |   1 +
 riscv/insns/mff_d.h     |   3 -
 riscv/insns/mff_s.h     |   2 -
 riscv/insns/mftx_d.h    |   3 +
 riscv/insns/mftx_s.h    |   2 +
 riscv/insns/mtf_d.h     |   3 -
 riscv/insns/mtf_s.h     |   2 -
 riscv/insns/mxtf_d.h    |   3 +
 riscv/insns/mxtf_s.h    |   2 +
 riscv/insns/s_b.h       |   1 -
 riscv/insns/s_d.h       |   2 -
 riscv/insns/s_h.h       |   1 -
 riscv/insns/s_w.h       |   1 -
 riscv/insns/sb.h        |   1 +
 riscv/insns/sd.h        |   2 +
 riscv/insns/sf_d.h      |   2 -
 riscv/insns/sf_w.h      |   2 -
 riscv/insns/sh.h        |   1 +
 riscv/insns/sw.h        |   1 +
 79 files changed, 190 insertions(+), 190 deletions(-)
 delete mode 100644 riscv/insns/fc_eq_d.h
 delete mode 100644 riscv/insns/fc_eq_s.h
 delete mode 100644 riscv/insns/fc_le_d.h
 delete mode 100644 riscv/insns/fc_le_s.h
 delete mode 100644 riscv/insns/fc_lt_d.h
 delete mode 100644 riscv/insns/fc_lt_s.h
 create mode 100644 riscv/insns/fcvt_d_lu.h
 create mode 100644 riscv/insns/fcvt_d_wu.h
 create mode 100644 riscv/insns/fcvt_lu_d.h
 create mode 100644 riscv/insns/fcvt_lu_s.h
 create mode 100644 riscv/insns/fcvt_s_lu.h
 create mode 100644 riscv/insns/fcvt_s_wu.h
 create mode 100644 riscv/insns/fcvt_wu_d.h
 create mode 100644 riscv/insns/fcvt_wu_s.h
 delete mode 100644 riscv/insns/fcvtu_d_l.h
 delete mode 100644 riscv/insns/fcvtu_d_w.h
 delete mode 100644 riscv/insns/fcvtu_l_d.h
 delete mode 100644 riscv/insns/fcvtu_l_s.h
 delete mode 100644 riscv/insns/fcvtu_s_l.h
 delete mode 100644 riscv/insns/fcvtu_s_w.h
 delete mode 100644 riscv/insns/fcvtu_w_d.h
 delete mode 100644 riscv/insns/fcvtu_w_s.h
 create mode 100644 riscv/insns/feq_d.h
 create mode 100644 riscv/insns/feq_s.h
 create mode 100644 riscv/insns/fld.h
 create mode 100644 riscv/insns/fle_d.h
 create mode 100644 riscv/insns/fle_s.h
 create mode 100644 riscv/insns/flt_d.h
 create mode 100644 riscv/insns/flt_s.h
 create mode 100644 riscv/insns/flw.h
 create mode 100644 riscv/insns/fsd.h
 create mode 100644 riscv/insns/fsgnj_d.h
 create mode 100644 riscv/insns/fsgnj_s.h
 create mode 100644 riscv/insns/fsgnjn_d.h
 create mode 100644 riscv/insns/fsgnjn_s.h
 create mode 100644 riscv/insns/fsgnjx_d.h
 create mode 100644 riscv/insns/fsgnjx_s.h
 delete mode 100644 riscv/insns/fsinj_d.h
 delete mode 100644 riscv/insns/fsinj_s.h
 delete mode 100644 riscv/insns/fsinjn_d.h
 delete mode 100644 riscv/insns/fsinjn_s.h
 delete mode 100644 riscv/insns/fsmul_d.h
 delete mode 100644 riscv/insns/fsmul_s.h
 create mode 100644 riscv/insns/fsw.h
 delete mode 100644 riscv/insns/l_b.h
 delete mode 100644 riscv/insns/l_bu.h
 delete mode 100644 riscv/insns/l_d.h
 delete mode 100644 riscv/insns/l_h.h
 delete mode 100644 riscv/insns/l_hu.h
 delete mode 100644 riscv/insns/l_w.h
 delete mode 100644 riscv/insns/l_wu.h
 create mode 100644 riscv/insns/lb.h
 create mode 100644 riscv/insns/lbu.h
 create mode 100644 riscv/insns/ld.h
 delete mode 100644 riscv/insns/lf_d.h
 delete mode 100644 riscv/insns/lf_w.h
 create mode 100644 riscv/insns/lh.h
 create mode 100644 riscv/insns/lhu.h
 create mode 100644 riscv/insns/lw.h
 create mode 100644 riscv/insns/lwu.h
 delete mode 100644 riscv/insns/mff_d.h
 delete mode 100644 riscv/insns/mff_s.h
 create mode 100644 riscv/insns/mftx_d.h
 create mode 100644 riscv/insns/mftx_s.h
 delete mode 100644 riscv/insns/mtf_d.h
 delete mode 100644 riscv/insns/mtf_s.h
 create mode 100644 riscv/insns/mxtf_d.h
 create mode 100644 riscv/insns/mxtf_s.h
 delete mode 100644 riscv/insns/s_b.h
 delete mode 100644 riscv/insns/s_d.h
 delete mode 100644 riscv/insns/s_h.h
 delete mode 100644 riscv/insns/s_w.h
 create mode 100644 riscv/insns/sb.h
 create mode 100644 riscv/insns/sd.h
 delete mode 100644 riscv/insns/sf_d.h
 delete mode 100644 riscv/insns/sf_w.h
 create mode 100644 riscv/insns/sh.h
 create mode 100644 riscv/insns/sw.h

diff --git a/riscv/execute.h b/riscv/execute.h
index f78375a..ab0fed7 100644
--- a/riscv/execute.h
+++ b/riscv/execute.h
@@ -27,37 +27,37 @@ switch((insn.bits >> 0x0) & 0x7f)
     {
       case 0x0:
       {
-        #include "insns/l_b.h"
+        #include "insns/lb.h"
         break;
       }
       case 0x1:
       {
-        #include "insns/l_h.h"
+        #include "insns/lh.h"
         break;
       }
       case 0x2:
       {
-        #include "insns/l_w.h"
+        #include "insns/lw.h"
         break;
       }
       case 0x3:
       {
-        #include "insns/l_d.h"
+        #include "insns/ld.h"
         break;
       }
       case 0x4:
       {
-        #include "insns/l_bu.h"
+        #include "insns/lbu.h"
         break;
       }
       case 0x5:
       {
-        #include "insns/l_hu.h"
+        #include "insns/lhu.h"
         break;
       }
       case 0x6:
       {
-        #include "insns/l_wu.h"
+        #include "insns/lwu.h"
         break;
       }
       default:
@@ -73,12 +73,12 @@ switch((insn.bits >> 0x0) & 0x7f)
     {
       case 0x2:
       {
-        #include "insns/lf_w.h"
+        #include "insns/flw.h"
         break;
       }
       case 0x3:
       {
-        #include "insns/lf_d.h"
+        #include "insns/fld.h"
         break;
       }
       default:
@@ -244,22 +244,22 @@ switch((insn.bits >> 0x0) & 0x7f)
     {
       case 0x0:
       {
-        #include "insns/s_b.h"
+        #include "insns/sb.h"
         break;
       }
       case 0x1:
       {
-        #include "insns/s_h.h"
+        #include "insns/sh.h"
         break;
       }
       case 0x2:
       {
-        #include "insns/s_w.h"
+        #include "insns/sw.h"
         break;
       }
       case 0x3:
       {
-        #include "insns/s_d.h"
+        #include "insns/sd.h"
         break;
       }
       default:
@@ -275,12 +275,12 @@ switch((insn.bits >> 0x0) & 0x7f)
     {
       case 0x2:
       {
-        #include "insns/sf_w.h"
+        #include "insns/fsw.h"
         break;
       }
       case 0x3:
       {
-        #include "insns/sf_d.h"
+        #include "insns/fsd.h"
         break;
       }
       default:
@@ -434,6 +434,11 @@ switch((insn.bits >> 0x0) & 0x7f)
     {
       case 0x0:
       {
+        if((insn.bits & 0x1ffff) == 0x43b)
+        {
+          #include "insns/mulw.h"
+          break;
+        }
         if((insn.bits & 0x1ffff) == 0x3b)
         {
           #include "insns/addw.h"
@@ -444,11 +449,6 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/subw.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x43b)
-        {
-          #include "insns/mulw.h"
-          break;
-        }
         #include "insns/unimp.h"
       }
       case 0x1:
@@ -588,11 +588,6 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/amomaxu_d.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x11c3)
-        {
-          #include "insns/amomin_d.h"
-          break;
-        }
         if((insn.bits & 0x1ffff) == 0x1c3)
         {
           #include "insns/amoadd_d.h"
@@ -613,6 +608,11 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/amoswap_d.h"
           break;
         }
+        if((insn.bits & 0x1ffff) == 0x11c3)
+        {
+          #include "insns/amomin_d.h"
+          break;
+        }
         #include "insns/unimp.h"
       }
       default:
@@ -691,6 +691,11 @@ switch((insn.bits >> 0x0) & 0x7f)
     {
       case 0x0:
       {
+        if((insn.bits & 0x3ff1ff) == 0x9053)
+        {
+          #include "insns/fcvt_lu_s.h"
+          break;
+        }
         if((insn.bits & 0x3ff1ff) == 0x11053)
         {
           #include "insns/fcvt_s_d.h"
@@ -706,11 +711,6 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/fcvt_s_w.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0xb053)
-        {
-          #include "insns/fcvtu_w_s.h"
-          break;
-        }
         if((insn.bits & 0x3ff1ff) == 0x8053)
         {
           #include "insns/fcvt_l_s.h"
@@ -721,11 +721,21 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/fdiv_s.h"
           break;
         }
+        if((insn.bits & 0x3ff1ff) == 0xd053)
+        {
+          #include "insns/fcvt_s_lu.h"
+          break;
+        }
         if((insn.bits & 0x1f1ff) == 0x2053)
         {
           #include "insns/fmul_s.h"
           break;
         }
+        if((insn.bits & 0x3ff1ff) == 0xb053)
+        {
+          #include "insns/fcvt_wu_s.h"
+          break;
+        }
         if((insn.bits & 0x3ff1ff) == 0xa053)
         {
           #include "insns/fcvt_w_s.h"
@@ -738,17 +748,7 @@ switch((insn.bits >> 0x0) & 0x7f)
         }
         if((insn.bits & 0x3ff1ff) == 0xf053)
         {
-          #include "insns/fcvtu_s_w.h"
-          break;
-        }
-        if((insn.bits & 0x3ff1ff) == 0xd053)
-        {
-          #include "insns/fcvtu_s_l.h"
-          break;
-        }
-        if((insn.bits & 0x3ff1ff) == 0x9053)
-        {
-          #include "insns/fcvtu_l_s.h"
+          #include "insns/fcvt_s_wu.h"
           break;
         }
         if((insn.bits & 0x3ff1ff) == 0xc053)
@@ -770,6 +770,11 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/fcvt_d_l.h"
           break;
         }
+        if((insn.bits & 0x3ff1ff) == 0x100d3)
+        {
+          #include "insns/fcvt_d_s.h"
+          break;
+        }
         if((insn.bits & 0x3ff1ff) == 0x80d3)
         {
           #include "insns/fcvt_l_d.h"
@@ -780,14 +785,19 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/fmul_d.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0xa0d3)
+        if((insn.bits & 0x3ff1ff) == 0xb0d3)
         {
-          #include "insns/fcvt_w_d.h"
+          #include "insns/fcvt_wu_d.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0xb0d3)
+        if((insn.bits & 0x3ff1ff) == 0xd0d3)
         {
-          #include "insns/fcvtu_w_d.h"
+          #include "insns/fcvt_d_lu.h"
+          break;
+        }
+        if((insn.bits & 0x3ff1ff) == 0xa0d3)
+        {
+          #include "insns/fcvt_w_d.h"
           break;
         }
         if((insn.bits & 0x1f1ff) == 0xd3)
@@ -797,7 +807,7 @@ switch((insn.bits >> 0x0) & 0x7f)
         }
         if((insn.bits & 0x3ff1ff) == 0x90d3)
         {
-          #include "insns/fcvtu_l_d.h"
+          #include "insns/fcvt_lu_d.h"
           break;
         }
         if((insn.bits & 0x1f1ff) == 0x10d3)
@@ -815,33 +825,23 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/fdiv_d.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0xd0d3)
-        {
-          #include "insns/fcvtu_d_l.h"
-          break;
-        }
         #include "insns/unimp.h"
       }
       case 0x4:
       {
-        if((insn.bits & 0x1ffff) == 0x6e53)
+        if((insn.bits & 0xf83fffff) == 0x1de53)
         {
-          #include "insns/fsinjn_s.h"
+          #include "insns/mtfsr.h"
           break;
         }
         if((insn.bits & 0x7c1ffff) == 0x18e53)
         {
-          #include "insns/mff_s.h"
+          #include "insns/mftx_s.h"
           break;
         }
-        if((insn.bits & 0xf83fffff) == 0x1de53)
-        {
-          #include "insns/mtfsr.h"
-          break;
-        }
-        if((insn.bits & 0x3fffff) == 0x1ce53)
+        if((insn.bits & 0x1ffff) == 0x17e53)
         {
-          #include "insns/mtf_s.h"
+          #include "insns/fle_s.h"
           break;
         }
         if((insn.bits & 0x7ffffff) == 0x1be53)
@@ -851,86 +851,86 @@ switch((insn.bits >> 0x0) & 0x7f)
         }
         if((insn.bits & 0x1ffff) == 0x16e53)
         {
-          #include "insns/fc_lt_s.h"
+          #include "insns/flt_s.h"
+          break;
+        }
+        if((insn.bits & 0x1ffff) == 0x15e53)
+        {
+          #include "insns/feq_s.h"
           break;
         }
         if((insn.bits & 0x1ffff) == 0x7e53)
         {
-          #include "insns/fsmul_s.h"
+          #include "insns/fsgnjx_s.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x5e53)
+        if((insn.bits & 0x3fffff) == 0x1ce53)
         {
-          #include "insns/fsinj_s.h"
+          #include "insns/mxtf_s.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x17e53)
+        if((insn.bits & 0x1ffff) == 0x5e53)
         {
-          #include "insns/fc_le_s.h"
+          #include "insns/fsgnj_s.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x15e53)
+        if((insn.bits & 0x1ffff) == 0x6e53)
         {
-          #include "insns/fc_eq_s.h"
+          #include "insns/fsgnjn_s.h"
           break;
         }
         #include "insns/unimp.h"
       }
       case 0x5:
       {
-        if((insn.bits & 0x7c1ffff) == 0x18ed3)
+        if((insn.bits & 0x3fffff) == 0xeed3)
         {
-          #include "insns/mff_d.h"
+          #include "insns/fcvt_d_w.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x6ed3)
+        if((insn.bits & 0x7c1ffff) == 0x18ed3)
         {
-          #include "insns/fsinjn_d.h"
+          #include "insns/mftx_d.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0xeed3)
+        if((insn.bits & 0x1ffff) == 0x17ed3)
         {
-          #include "insns/fcvt_d_w.h"
+          #include "insns/fle_d.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0x10ed3)
+        if((insn.bits & 0x1ffff) == 0x16ed3)
         {
-          #include "insns/fcvt_d_s.h"
+          #include "insns/flt_d.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0x1ced3)
+        if((insn.bits & 0x1ffff) == 0x7ed3)
         {
-          #include "insns/mtf_d.h"
+          #include "insns/fsgnjx_d.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0xfed3)
+        if((insn.bits & 0x1ffff) == 0x15ed3)
         {
-          #include "insns/fcvtu_d_w.h"
+          #include "insns/feq_d.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x16ed3)
+        if((insn.bits & 0x3fffff) == 0xfed3)
         {
-          #include "insns/fc_lt_d.h"
+          #include "insns/fcvt_d_wu.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x15ed3)
+        if((insn.bits & 0x1ffff) == 0x6ed3)
         {
-          #include "insns/fc_eq_d.h"
+          #include "insns/fsgnjn_d.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x7ed3)
+        if((insn.bits & 0x3fffff) == 0x1ced3)
         {
-          #include "insns/fsmul_d.h"
+          #include "insns/mxtf_d.h"
           break;
         }
         if((insn.bits & 0x1ffff) == 0x5ed3)
         {
-          #include "insns/fsinj_d.h"
-          break;
-        }
-        if((insn.bits & 0x1ffff) == 0x17ed3)
-        {
-          #include "insns/fc_le_d.h"
+          #include "insns/fsgnj_d.h"
           break;
         }
         #include "insns/unimp.h"
diff --git a/riscv/insns/fc_eq_d.h b/riscv/insns/fc_eq_d.h
deleted file mode 100644
index 9db8760..0000000
--- a/riscv/insns/fc_eq_d.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_fp;
-RD = f64_eq(FRS1, FRS2);
-set_fp_exceptions;
diff --git a/riscv/insns/fc_eq_s.h b/riscv/insns/fc_eq_s.h
deleted file mode 100644
index 658e8f6..0000000
--- a/riscv/insns/fc_eq_s.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_fp;
-RD = f32_eq(FRS1, FRS2);
-set_fp_exceptions;
diff --git a/riscv/insns/fc_le_d.h b/riscv/insns/fc_le_d.h
deleted file mode 100644
index da76187..0000000
--- a/riscv/insns/fc_le_d.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_fp;
-RD = f64_le(FRS1, FRS2);
-set_fp_exceptions;
diff --git a/riscv/insns/fc_le_s.h b/riscv/insns/fc_le_s.h
deleted file mode 100644
index 9c83a17..0000000
--- a/riscv/insns/fc_le_s.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_fp;
-RD = f32_le(FRS1, FRS2);
-set_fp_exceptions;
diff --git a/riscv/insns/fc_lt_d.h b/riscv/insns/fc_lt_d.h
deleted file mode 100644
index 01d135a..0000000
--- a/riscv/insns/fc_lt_d.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_fp;
-RD = f64_lt(FRS1, FRS2);
-set_fp_exceptions;
diff --git a/riscv/insns/fc_lt_s.h b/riscv/insns/fc_lt_s.h
deleted file mode 100644
index 52eee5d..0000000
--- a/riscv/insns/fc_lt_s.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_fp;
-RD = f32_lt(FRS1, FRS2);
-set_fp_exceptions;
diff --git a/riscv/insns/fcvt_d_lu.h b/riscv/insns/fcvt_d_lu.h
new file mode 100644
index 0000000..68c0482
--- /dev/null
+++ b/riscv/insns/fcvt_d_lu.h
@@ -0,0 +1,5 @@
+require_xpr64;
+require_fp;
+softfloat_roundingMode = RM;
+FRD = i64_to_f64(RS1);
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_d_wu.h b/riscv/insns/fcvt_d_wu.h
new file mode 100644
index 0000000..2757790
--- /dev/null
+++ b/riscv/insns/fcvt_d_wu.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+FRD = ui32_to_f64(RS1);
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_lu_d.h b/riscv/insns/fcvt_lu_d.h
new file mode 100644
index 0000000..bd460d5
--- /dev/null
+++ b/riscv/insns/fcvt_lu_d.h
@@ -0,0 +1,5 @@
+require_xpr64;
+require_fp;
+softfloat_roundingMode = RM;
+RD = f64_to_i64_r_minMag(FRS1,true);
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_lu_s.h b/riscv/insns/fcvt_lu_s.h
new file mode 100644
index 0000000..1ed4594
--- /dev/null
+++ b/riscv/insns/fcvt_lu_s.h
@@ -0,0 +1,5 @@
+require_xpr64;
+require_fp;
+softfloat_roundingMode = RM;
+RD = f32_to_i64_r_minMag(FRS1,true);
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_s_lu.h b/riscv/insns/fcvt_s_lu.h
new file mode 100644
index 0000000..f149229
--- /dev/null
+++ b/riscv/insns/fcvt_s_lu.h
@@ -0,0 +1,5 @@
+require_xpr64;
+require_fp;
+softfloat_roundingMode = RM;
+FRD = i64_to_f32(RS1);
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_s_wu.h b/riscv/insns/fcvt_s_wu.h
new file mode 100644
index 0000000..4c53c01
--- /dev/null
+++ b/riscv/insns/fcvt_s_wu.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+FRD = ui32_to_f32(RS1);
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_wu_d.h b/riscv/insns/fcvt_wu_d.h
new file mode 100644
index 0000000..93860e8
--- /dev/null
+++ b/riscv/insns/fcvt_wu_d.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+RD = f64_to_ui32_r_minMag(FRS1,true);
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_wu_s.h b/riscv/insns/fcvt_wu_s.h
new file mode 100644
index 0000000..04b8fb2
--- /dev/null
+++ b/riscv/insns/fcvt_wu_s.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+RD = f32_to_ui32_r_minMag(FRS1,true);
+set_fp_exceptions;
diff --git a/riscv/insns/fcvtu_d_l.h b/riscv/insns/fcvtu_d_l.h
deleted file mode 100644
index 68c0482..0000000
--- a/riscv/insns/fcvtu_d_l.h
+++ /dev/null
@@ -1,5 +0,0 @@
-require_xpr64;
-require_fp;
-softfloat_roundingMode = RM;
-FRD = i64_to_f64(RS1);
-set_fp_exceptions;
diff --git a/riscv/insns/fcvtu_d_w.h b/riscv/insns/fcvtu_d_w.h
deleted file mode 100644
index 2757790..0000000
--- a/riscv/insns/fcvtu_d_w.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = ui32_to_f64(RS1);
-set_fp_exceptions;
diff --git a/riscv/insns/fcvtu_l_d.h b/riscv/insns/fcvtu_l_d.h
deleted file mode 100644
index bd460d5..0000000
--- a/riscv/insns/fcvtu_l_d.h
+++ /dev/null
@@ -1,5 +0,0 @@
-require_xpr64;
-require_fp;
-softfloat_roundingMode = RM;
-RD = f64_to_i64_r_minMag(FRS1,true);
-set_fp_exceptions;
diff --git a/riscv/insns/fcvtu_l_s.h b/riscv/insns/fcvtu_l_s.h
deleted file mode 100644
index 1ed4594..0000000
--- a/riscv/insns/fcvtu_l_s.h
+++ /dev/null
@@ -1,5 +0,0 @@
-require_xpr64;
-require_fp;
-softfloat_roundingMode = RM;
-RD = f32_to_i64_r_minMag(FRS1,true);
-set_fp_exceptions;
diff --git a/riscv/insns/fcvtu_s_l.h b/riscv/insns/fcvtu_s_l.h
deleted file mode 100644
index f149229..0000000
--- a/riscv/insns/fcvtu_s_l.h
+++ /dev/null
@@ -1,5 +0,0 @@
-require_xpr64;
-require_fp;
-softfloat_roundingMode = RM;
-FRD = i64_to_f32(RS1);
-set_fp_exceptions;
diff --git a/riscv/insns/fcvtu_s_w.h b/riscv/insns/fcvtu_s_w.h
deleted file mode 100644
index 4c53c01..0000000
--- a/riscv/insns/fcvtu_s_w.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = ui32_to_f32(RS1);
-set_fp_exceptions;
diff --git a/riscv/insns/fcvtu_w_d.h b/riscv/insns/fcvtu_w_d.h
deleted file mode 100644
index 93860e8..0000000
--- a/riscv/insns/fcvtu_w_d.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-RD = f64_to_ui32_r_minMag(FRS1,true);
-set_fp_exceptions;
diff --git a/riscv/insns/fcvtu_w_s.h b/riscv/insns/fcvtu_w_s.h
deleted file mode 100644
index 04b8fb2..0000000
--- a/riscv/insns/fcvtu_w_s.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-RD = f32_to_ui32_r_minMag(FRS1,true);
-set_fp_exceptions;
diff --git a/riscv/insns/feq_d.h b/riscv/insns/feq_d.h
new file mode 100644
index 0000000..9db8760
--- /dev/null
+++ b/riscv/insns/feq_d.h
@@ -0,0 +1,3 @@
+require_fp;
+RD = f64_eq(FRS1, FRS2);
+set_fp_exceptions;
diff --git a/riscv/insns/feq_s.h b/riscv/insns/feq_s.h
new file mode 100644
index 0000000..658e8f6
--- /dev/null
+++ b/riscv/insns/feq_s.h
@@ -0,0 +1,3 @@
+require_fp;
+RD = f32_eq(FRS1, FRS2);
+set_fp_exceptions;
diff --git a/riscv/insns/fld.h b/riscv/insns/fld.h
new file mode 100644
index 0000000..123dea4
--- /dev/null
+++ b/riscv/insns/fld.h
@@ -0,0 +1,2 @@
+require_fp;
+FRD = mmu.load_int64(RS1+SIMM);
diff --git a/riscv/insns/fle_d.h b/riscv/insns/fle_d.h
new file mode 100644
index 0000000..da76187
--- /dev/null
+++ b/riscv/insns/fle_d.h
@@ -0,0 +1,3 @@
+require_fp;
+RD = f64_le(FRS1, FRS2);
+set_fp_exceptions;
diff --git a/riscv/insns/fle_s.h b/riscv/insns/fle_s.h
new file mode 100644
index 0000000..9c83a17
--- /dev/null
+++ b/riscv/insns/fle_s.h
@@ -0,0 +1,3 @@
+require_fp;
+RD = f32_le(FRS1, FRS2);
+set_fp_exceptions;
diff --git a/riscv/insns/flt_d.h b/riscv/insns/flt_d.h
new file mode 100644
index 0000000..01d135a
--- /dev/null
+++ b/riscv/insns/flt_d.h
@@ -0,0 +1,3 @@
+require_fp;
+RD = f64_lt(FRS1, FRS2);
+set_fp_exceptions;
diff --git a/riscv/insns/flt_s.h b/riscv/insns/flt_s.h
new file mode 100644
index 0000000..52eee5d
--- /dev/null
+++ b/riscv/insns/flt_s.h
@@ -0,0 +1,3 @@
+require_fp;
+RD = f32_lt(FRS1, FRS2);
+set_fp_exceptions;
diff --git a/riscv/insns/flw.h b/riscv/insns/flw.h
new file mode 100644
index 0000000..335fd7d
--- /dev/null
+++ b/riscv/insns/flw.h
@@ -0,0 +1,2 @@
+require_fp;
+FRD = mmu.load_int32(RS1+SIMM);
diff --git a/riscv/insns/fsd.h b/riscv/insns/fsd.h
new file mode 100644
index 0000000..113398e
--- /dev/null
+++ b/riscv/insns/fsd.h
@@ -0,0 +1,2 @@
+require_fp;
+mmu.store_uint64(RS1+BIMM, FRS2);
diff --git a/riscv/insns/fsgnj_d.h b/riscv/insns/fsgnj_d.h
new file mode 100644
index 0000000..f66e804
--- /dev/null
+++ b/riscv/insns/fsgnj_d.h
@@ -0,0 +1,2 @@
+require_fp;
+FRD = (FRS1 &~ INT64_MIN) | (FRS2 & INT64_MIN);
diff --git a/riscv/insns/fsgnj_s.h b/riscv/insns/fsgnj_s.h
new file mode 100644
index 0000000..35609ac
--- /dev/null
+++ b/riscv/insns/fsgnj_s.h
@@ -0,0 +1,2 @@
+require_fp;
+FRD = (FRS1 &~ (uint32_t)INT32_MIN) | (FRS2 & (uint32_t)INT32_MIN);
diff --git a/riscv/insns/fsgnjn_d.h b/riscv/insns/fsgnjn_d.h
new file mode 100644
index 0000000..22de215
--- /dev/null
+++ b/riscv/insns/fsgnjn_d.h
@@ -0,0 +1,2 @@
+require_fp;
+FRD = (FRS1 &~ INT64_MIN) | ((~FRS2) & INT64_MIN);
diff --git a/riscv/insns/fsgnjn_s.h b/riscv/insns/fsgnjn_s.h
new file mode 100644
index 0000000..dd66d71
--- /dev/null
+++ b/riscv/insns/fsgnjn_s.h
@@ -0,0 +1,2 @@
+require_fp;
+FRD = (FRS1 &~ (uint32_t)INT32_MIN) | ((~FRS2) & (uint32_t)INT32_MIN);
diff --git a/riscv/insns/fsgnjx_d.h b/riscv/insns/fsgnjx_d.h
new file mode 100644
index 0000000..331b6e4
--- /dev/null
+++ b/riscv/insns/fsgnjx_d.h
@@ -0,0 +1,2 @@
+require_fp;
+FRD = FRS1 ^ (FRS2 & INT64_MIN);
diff --git a/riscv/insns/fsgnjx_s.h b/riscv/insns/fsgnjx_s.h
new file mode 100644
index 0000000..b455406
--- /dev/null
+++ b/riscv/insns/fsgnjx_s.h
@@ -0,0 +1,2 @@
+require_fp;
+FRD = FRS1 ^ (FRS2 & (uint32_t)INT32_MIN);
diff --git a/riscv/insns/fsinj_d.h b/riscv/insns/fsinj_d.h
deleted file mode 100644
index f66e804..0000000
--- a/riscv/insns/fsinj_d.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_fp;
-FRD = (FRS1 &~ INT64_MIN) | (FRS2 & INT64_MIN);
diff --git a/riscv/insns/fsinj_s.h b/riscv/insns/fsinj_s.h
deleted file mode 100644
index 35609ac..0000000
--- a/riscv/insns/fsinj_s.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_fp;
-FRD = (FRS1 &~ (uint32_t)INT32_MIN) | (FRS2 & (uint32_t)INT32_MIN);
diff --git a/riscv/insns/fsinjn_d.h b/riscv/insns/fsinjn_d.h
deleted file mode 100644
index 22de215..0000000
--- a/riscv/insns/fsinjn_d.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_fp;
-FRD = (FRS1 &~ INT64_MIN) | ((~FRS2) & INT64_MIN);
diff --git a/riscv/insns/fsinjn_s.h b/riscv/insns/fsinjn_s.h
deleted file mode 100644
index dd66d71..0000000
--- a/riscv/insns/fsinjn_s.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_fp;
-FRD = (FRS1 &~ (uint32_t)INT32_MIN) | ((~FRS2) & (uint32_t)INT32_MIN);
diff --git a/riscv/insns/fsmul_d.h b/riscv/insns/fsmul_d.h
deleted file mode 100644
index 331b6e4..0000000
--- a/riscv/insns/fsmul_d.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_fp;
-FRD = FRS1 ^ (FRS2 & INT64_MIN);
diff --git a/riscv/insns/fsmul_s.h b/riscv/insns/fsmul_s.h
deleted file mode 100644
index b455406..0000000
--- a/riscv/insns/fsmul_s.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_fp;
-FRD = FRS1 ^ (FRS2 & (uint32_t)INT32_MIN);
diff --git a/riscv/insns/fsw.h b/riscv/insns/fsw.h
new file mode 100644
index 0000000..23d3333
--- /dev/null
+++ b/riscv/insns/fsw.h
@@ -0,0 +1,2 @@
+require_fp;
+mmu.store_uint32(RS1+BIMM, FRS2);
diff --git a/riscv/insns/l_b.h b/riscv/insns/l_b.h
deleted file mode 100644
index 81ba7de..0000000
--- a/riscv/insns/l_b.h
+++ /dev/null
@@ -1 +0,0 @@
-RD = mmu.load_int8(RS1+SIMM);
diff --git a/riscv/insns/l_bu.h b/riscv/insns/l_bu.h
deleted file mode 100644
index 12c688a..0000000
--- a/riscv/insns/l_bu.h
+++ /dev/null
@@ -1 +0,0 @@
-RD = mmu.load_uint8(RS1+SIMM);
diff --git a/riscv/insns/l_d.h b/riscv/insns/l_d.h
deleted file mode 100644
index 940d348..0000000
--- a/riscv/insns/l_d.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_xpr64;
-RD = mmu.load_int64(RS1+SIMM);
diff --git a/riscv/insns/l_h.h b/riscv/insns/l_h.h
deleted file mode 100644
index ec25bc4..0000000
--- a/riscv/insns/l_h.h
+++ /dev/null
@@ -1 +0,0 @@
-RD = mmu.load_int16(RS1+SIMM);
diff --git a/riscv/insns/l_hu.h b/riscv/insns/l_hu.h
deleted file mode 100644
index 0999c00..0000000
--- a/riscv/insns/l_hu.h
+++ /dev/null
@@ -1 +0,0 @@
-RD = mmu.load_uint16(RS1+SIMM);
diff --git a/riscv/insns/l_w.h b/riscv/insns/l_w.h
deleted file mode 100644
index 769c9fd..0000000
--- a/riscv/insns/l_w.h
+++ /dev/null
@@ -1 +0,0 @@
-RD = mmu.load_int32(RS1+SIMM);
diff --git a/riscv/insns/l_wu.h b/riscv/insns/l_wu.h
deleted file mode 100644
index 5e62b0f..0000000
--- a/riscv/insns/l_wu.h
+++ /dev/null
@@ -1 +0,0 @@
-RD = mmu.load_uint32(RS1+SIMM);
diff --git a/riscv/insns/lb.h b/riscv/insns/lb.h
new file mode 100644
index 0000000..81ba7de
--- /dev/null
+++ b/riscv/insns/lb.h
@@ -0,0 +1 @@
+RD = mmu.load_int8(RS1+SIMM);
diff --git a/riscv/insns/lbu.h b/riscv/insns/lbu.h
new file mode 100644
index 0000000..12c688a
--- /dev/null
+++ b/riscv/insns/lbu.h
@@ -0,0 +1 @@
+RD = mmu.load_uint8(RS1+SIMM);
diff --git a/riscv/insns/ld.h b/riscv/insns/ld.h
new file mode 100644
index 0000000..940d348
--- /dev/null
+++ b/riscv/insns/ld.h
@@ -0,0 +1,2 @@
+require_xpr64;
+RD = mmu.load_int64(RS1+SIMM);
diff --git a/riscv/insns/lf_d.h b/riscv/insns/lf_d.h
deleted file mode 100644
index 123dea4..0000000
--- a/riscv/insns/lf_d.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_fp;
-FRD = mmu.load_int64(RS1+SIMM);
diff --git a/riscv/insns/lf_w.h b/riscv/insns/lf_w.h
deleted file mode 100644
index 335fd7d..0000000
--- a/riscv/insns/lf_w.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_fp;
-FRD = mmu.load_int32(RS1+SIMM);
diff --git a/riscv/insns/lh.h b/riscv/insns/lh.h
new file mode 100644
index 0000000..ec25bc4
--- /dev/null
+++ b/riscv/insns/lh.h
@@ -0,0 +1 @@
+RD = mmu.load_int16(RS1+SIMM);
diff --git a/riscv/insns/lhu.h b/riscv/insns/lhu.h
new file mode 100644
index 0000000..0999c00
--- /dev/null
+++ b/riscv/insns/lhu.h
@@ -0,0 +1 @@
+RD = mmu.load_uint16(RS1+SIMM);
diff --git a/riscv/insns/lw.h b/riscv/insns/lw.h
new file mode 100644
index 0000000..769c9fd
--- /dev/null
+++ b/riscv/insns/lw.h
@@ -0,0 +1 @@
+RD = mmu.load_int32(RS1+SIMM);
diff --git a/riscv/insns/lwu.h b/riscv/insns/lwu.h
new file mode 100644
index 0000000..5e62b0f
--- /dev/null
+++ b/riscv/insns/lwu.h
@@ -0,0 +1 @@
+RD = mmu.load_uint32(RS1+SIMM);
diff --git a/riscv/insns/mff_d.h b/riscv/insns/mff_d.h
deleted file mode 100644
index 31be4cb..0000000
--- a/riscv/insns/mff_d.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_xpr64;
-require_fp;
-RD = FRS2;
diff --git a/riscv/insns/mff_s.h b/riscv/insns/mff_s.h
deleted file mode 100644
index 589b33b..0000000
--- a/riscv/insns/mff_s.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_fp;
-RD = sext32(FRS2);
diff --git a/riscv/insns/mftx_d.h b/riscv/insns/mftx_d.h
new file mode 100644
index 0000000..31be4cb
--- /dev/null
+++ b/riscv/insns/mftx_d.h
@@ -0,0 +1,3 @@
+require_xpr64;
+require_fp;
+RD = FRS2;
diff --git a/riscv/insns/mftx_s.h b/riscv/insns/mftx_s.h
new file mode 100644
index 0000000..589b33b
--- /dev/null
+++ b/riscv/insns/mftx_s.h
@@ -0,0 +1,2 @@
+require_fp;
+RD = sext32(FRS2);
diff --git a/riscv/insns/mtf_d.h b/riscv/insns/mtf_d.h
deleted file mode 100644
index 29792ec..0000000
--- a/riscv/insns/mtf_d.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_xpr64;
-require_fp;
-FRD = RS1;
diff --git a/riscv/insns/mtf_s.h b/riscv/insns/mtf_s.h
deleted file mode 100644
index 54546ea..0000000
--- a/riscv/insns/mtf_s.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_fp;
-FRD = RS1;
diff --git a/riscv/insns/mxtf_d.h b/riscv/insns/mxtf_d.h
new file mode 100644
index 0000000..29792ec
--- /dev/null
+++ b/riscv/insns/mxtf_d.h
@@ -0,0 +1,3 @@
+require_xpr64;
+require_fp;
+FRD = RS1;
diff --git a/riscv/insns/mxtf_s.h b/riscv/insns/mxtf_s.h
new file mode 100644
index 0000000..54546ea
--- /dev/null
+++ b/riscv/insns/mxtf_s.h
@@ -0,0 +1,2 @@
+require_fp;
+FRD = RS1;
diff --git a/riscv/insns/s_b.h b/riscv/insns/s_b.h
deleted file mode 100644
index af5bd10..0000000
--- a/riscv/insns/s_b.h
+++ /dev/null
@@ -1 +0,0 @@
-mmu.store_uint8(RS1+BIMM, RS2);
diff --git a/riscv/insns/s_d.h b/riscv/insns/s_d.h
deleted file mode 100644
index 2009149..0000000
--- a/riscv/insns/s_d.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_xpr64;
-mmu.store_uint64(RS1+BIMM, RS2);
diff --git a/riscv/insns/s_h.h b/riscv/insns/s_h.h
deleted file mode 100644
index a484e1e..0000000
--- a/riscv/insns/s_h.h
+++ /dev/null
@@ -1 +0,0 @@
-mmu.store_uint16(RS1+BIMM, RS2);
diff --git a/riscv/insns/s_w.h b/riscv/insns/s_w.h
deleted file mode 100644
index dbe260f..0000000
--- a/riscv/insns/s_w.h
+++ /dev/null
@@ -1 +0,0 @@
-mmu.store_uint32(RS1+BIMM, RS2);
diff --git a/riscv/insns/sb.h b/riscv/insns/sb.h
new file mode 100644
index 0000000..af5bd10
--- /dev/null
+++ b/riscv/insns/sb.h
@@ -0,0 +1 @@
+mmu.store_uint8(RS1+BIMM, RS2);
diff --git a/riscv/insns/sd.h b/riscv/insns/sd.h
new file mode 100644
index 0000000..2009149
--- /dev/null
+++ b/riscv/insns/sd.h
@@ -0,0 +1,2 @@
+require_xpr64;
+mmu.store_uint64(RS1+BIMM, RS2);
diff --git a/riscv/insns/sf_d.h b/riscv/insns/sf_d.h
deleted file mode 100644
index 113398e..0000000
--- a/riscv/insns/sf_d.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_fp;
-mmu.store_uint64(RS1+BIMM, FRS2);
diff --git a/riscv/insns/sf_w.h b/riscv/insns/sf_w.h
deleted file mode 100644
index 23d3333..0000000
--- a/riscv/insns/sf_w.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_fp;
-mmu.store_uint32(RS1+BIMM, FRS2);
diff --git a/riscv/insns/sh.h b/riscv/insns/sh.h
new file mode 100644
index 0000000..a484e1e
--- /dev/null
+++ b/riscv/insns/sh.h
@@ -0,0 +1 @@
+mmu.store_uint16(RS1+BIMM, RS2);
diff --git a/riscv/insns/sw.h b/riscv/insns/sw.h
new file mode 100644
index 0000000..dbe260f
--- /dev/null
+++ b/riscv/insns/sw.h
@@ -0,0 +1 @@
+mmu.store_uint32(RS1+BIMM, RS2);
-- 
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