rocket-tools/riscv-gnu-toolchain/spike.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2019-06-04	rvv: add vfrsub.vf	Chih-Min Chao	1	-0/+1
2019-06-04	rvv: change vfeq to vmfeq and related comparision instruction	Chih-Min Chao	1	-7/+7
2019-05-29	rvv: disasm: remove unused include	Chih-Min Chao	1	-1/+0
2019-05-29	Clean up debug module options. (#299)	Tim Newsome	1	-25/+31
2019-05-29	rvv: disas: add fault-first instructions	Chih-Min Chao	1	-14/+30
2019-05-27	rvv: disasm: shift should use unsiged vi	Chih-Min Chao	1	-6/+6
2019-05-23	rvv: fix rgather	Chih-Min Chao	1	-1/+1
2019-05-22	rvv: fix compress	Chih-Min Chao	1	-1/+1
2019-05-21	rvv: disasm: fix vmsbf/sof/sif/vid operand	Chih-Min Chao	1	-4/+4
2019-05-20	rvv: change viota_m to vmiota_m	Chih-Min Chao	1	-1/+1
2019-05-20	rvv: add --check-1905 option to turn on 1905 release check	Chih-Min Chao	1	-0/+5
2019-05-19	rvv: separate vmuary0 by new encoding change	Chih-Min Chao	1	-10/+7
2019-05-16	rvv: fix integer reduction instruction suffix	Chih-Min Chao	1	-8/+8
2019-05-16	rvv: disas: fix seg ld/st suffix	Chih-Min Chao	1	-35/+35
2019-05-16	rvv: disas: fix segment load/store	Chih-Min Chao	1	-52/+51
2019-05-14	Add --debug-no-abstract-csr (#267)	Tim Newsome	1	-1/+5
2019-05-14	Implement debug hasel support (#287)	Tim Newsome	1	-1/+5
2019-05-14	Version 1.0.0	Andrew Waterman	1	-0/+2
2019-05-14	Add fesvr; only globally install fesvr headers/libs	Andrew Waterman	1	-0/+1
2019-05-14	Make --help return 0 after printing the help message	Andrew Waterman	1	-4/+11
2019-05-13	Revert "Add FLH and FSH instructions expanding IEEE fp16 in memory to fp32 in...	Chih-Min Chao	1	-2/+0
2019-05-10	rvv: disasm: firx vfunary1 mask	Chih-Min Chao	1	-4/+4
2019-05-09	Add a tool "spike-log-parser" to get the instruction name from spike log.	Jerry Shih	2	-0/+61
2019-04-30	rvv: spike-dasm doens't support configurable vector yet.	Dave.Wen	1	-1/+1
2019-04-30	rvv: configurable vector architecture during configuration and	Dave.Wen	1	-1/+4
2019-04-29	rvv: disasm: fix vmunary0	Chih-Min Chao	1	-10/+10
2019-04-28	rvv: disasm: fix vfcvt	Chih-Min Chao	1	-5/+5
2019-04-24	rvv: fix sign-injection naming	Chih-Min Chao	1	-2/+2
2019-04-24	rvv: disas: add vmunary0	Chih-Min Chao	1	-0/+10
2019-04-24	rvv: disas: add vfunary0/1	Chih-Min Chao	1	-2/+26
2019-04-24	rvv: disas: use existing macro	Chih-Min Chao	1	-4/+2
2019-04-24	rvv: disas: use correct macro prefix	Chih-Min Chao	1	-176/+176
2019-04-24	rvv: disas: use existing macro	Chih-Min Chao	1	-11/+5
2019-04-19	rvv: disasm: floating instruction use freg	Chih-Min Chao	1	-5/+5
2019-04-18	disasm: add vsetvl disasm support	Dave	1	-0/+1
2019-04-17	disasm: handle most of vector alu instruction	Chih-Min Chao	1	-52/+267
2019-04-17	disasm: handle vector unit/stride/index ld/st with segment variation	Chih-Min Chao	1	-16/+127
2019-04-07	desasm: WIP	Dave.Wen	1	-0/+16
2019-04-06	Add --dmi-rti and --abstract-rti to test OpenOCD.	Tim Newsome	1	-2/+14
2019-04-03	disasm: for debugging purpose, I added some vector alu insts	Dave.Wen	1	-0/+27
2019-04-02	disasm: add disasm for vector instructions	Dave.Wen	1	-0/+4
2019-03-26	rvv: merge vssseg[3-6]w.v into vssw.v	Chih-Min Chao	1	-4/+5
2019-03-26	rvv: merge vlsseg[3-6]w.v into vlsw.v	Chih-Min Chao	1	-4/+5
2019-03-25	rvv: merge vsseg[3-6]w.v into vsw.v	Chih-Min Chao	1	-1/+1
2019-03-25	disam: use correct code for vlsseg[3-6w.v naming	Chih-Min Chao	1	-8/+8
2019-03-25	rvv: merge vlseg[3-6]w.v into vlw.v	Chih-Min Chao	1	-1/+1
2019-02-24	implement disassembly of instructions used by demo kernels	Bruce Hoult	1	-0/+76
2019-01-21	Add FLH and FSH instructions expanding IEEE fp16 in memory to fp32 in registers	Bruce Hoult	1	-0/+2
2018-10-03	fix disassembly of c.addi4spn	Andrew Waterman	1	-1/+1
2018-09-24	Add "--log-cache-miss" option to generate a log of cache miss. (#241)	takeoverjp	1	-0/+5