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2020-05-22rvv: disasm: fix vsetvliChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-19fdt: restructure dtb create and config flowChih-Min Chao1-3/+1
1. pass dtb option from constructor 2. separate dtb generation from rom initialization 3. setup clint base from dtb Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-19fdt: option: add --dtb option to specify dtb binary fileChih-Min Chao1-0/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-19fdt: import fdt library from OpenSBIChih-Min Chao1-0/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-18rvv: disasm: add missing .wx formatChih-Min Chao1-1/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-18rvv: disasm: fix unorder index storeChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-14rvv: disasm: fix amo formatChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-14disasm: refine structure nameChih-Min Chao1-3/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-14rvv: add lmul=1 (m0) in disasm messageDave.Wen1-19/+17
2020-05-14rvv: fix the fractional lmulDave.Wen1-3/+3
2020-05-13rvv: change to 0.9amoChih-Min Chao1-19/+36
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-13rvv: amo pre-0.9Chih-Min Chao1-0/+27
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-13rvv: fractional_lmul when lmul < 1Dave.Wen1-2/+22
2020-05-13vtype: fix the vta and vma functions and debugging displayDave.Wen1-0/+3
2020-05-12rvv: add ext opcodeChih-Min Chao1-0/+8
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-12rvv: op: change vfunary0 and funary1 func6 fieldChih-Min Chao1-3/+9
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-11rvv: change to 0.9 ldstChih-Min Chao1-65/+58
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-04zfh: add fp16 disasmChih-Min Chao1-0/+38
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-16rvv: fix rtz cvtChih-Min Chao1-2/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-14rvv: disasm: leave only SEW-bit segment load/storeChih-Min Chao1-66/+0
new features in spec 0.9 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-14rvv: add vfslide1[down|up].vf and refine checking ruleChih-Min Chao1-0/+2
new features in spec 0.9 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-14rvv: add float conversion for rtz variantsChih-Min Chao1-1/+7
new features in spec 0.9 ref: https://github.com/riscv/riscv-v-spec/issues/352 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-14Handle misaligned memories by aligning them, rather than erroringAndrew Waterman1-1/+16
Resolves #442
2020-04-14Revert "rvv: support simulations with mem size <4K"Chih-Min Chao1-1/+1
This reverts commit 109aa23bbf8aba76b27629095688e86643eaf51f. There is new implementation
2020-04-07rvv: support simulations with mem size <4KDave.Wen1-1/+1
2020-04-05Write execution logs to a named log file (#409)Rupert Swarbrick2-5/+8
This patch adds a --log argument to spike. If not given, the behaviour is unchanged: messages logging execution of instructions and (if commit logging is enabled) commits go to stderr. If --log=P is given, Spike now writes these messages to a log file at the path P. This is nice, because they are no longer tangled up with other errors and warnings. The code is mostly plumbing: passing a FILE* object through to the functions that were using stderr. I've written a simple "log_file_t" class, which opens a log file if necessary and yields it or stderr.
2020-03-04rvv: remove the option of vector misaligned accessZhen Wei1-3/+0
2020-03-04rvv: remove the option of vector impl. checkZhen Wei1-32/+0
The check is not needed anymore since most vector kernels are supported in current implemented vector instruction set.
2020-02-19Add optional support for real-time clintAnup Patel1-1/+5
This patch adds optional support clint timer incrementing at real-time rate. This can be enabled by passing command line parameter "--real-time-clint". This feature can be used for: 1. Checking whether any code addition to Spike is slowing down simulation too much 2. Comparing run-time for software on Spike with other functional simulators (such as QEMU) Signed-off-by: Anup Patel <anup.patel@wdc.com>
2020-02-19Make spike capable of booting LinuxAnup Patel1-1/+39
Latest Linux does not boot Spike mainly because: 1. Spike does not set bootargs in DTS 2. Spike does not provide mechanism to load initrd for Linux This patch addresses both above issues and we can now get latest Linux to prompt on Spike. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-02-12Fix immediate signedness in vector disassemblyAndrew Waterman1-3/+3
2020-02-12Decouple spike-dasm program from simulator codeAndrew Waterman1-4/+21
2020-01-06rvv : vmv[1248]r.vChih-Min Chao1-4/+9
simple register copy instructions Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-12-12rvv: fix vfwcvt/vfncvt for f32 -> f64 and f64 -> f32Chih-Min Chao1-11/+9
1. fix disam 2. refine checking rule and move them out of loop 3. add missing exception keeping for each element Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-27rvv: add whole register load/store, vl1r.v/vs1r.vChih-Min Chao1-11/+11
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-27rvv: replace vn suffic by 'w'Chih-Min Chao1-26/+30
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-27rvv: add load/store whole registerChih-Min Chao1-0/+4
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-27rvv: rename vfncvt suffix and add rod rouding typeChih-Min Chao1-15/+21
1. vfncvt*.v -> vfncvt*.w 2. add vfncvt.rod.f.f.w Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-27rvv: add quad insn and new vlenb csrChih-Min Chao1-5/+5
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-17add vaaddu/vasubu/vfncvt.rod.f.f.v to diassemblerAndrew Waterman1-2/+5
2019-11-17Add --priv option to control which privilege modes are availableAndrew Waterman3-3/+6
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-10-22rvv: remove vmfordChih-Min Chao1-1/+0
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-10-14rvv: update encoding to v0.8Chih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-10-08Speed up compilation of disasm.cc, especially in clangAndrew Waterman1-1/+1
2019-09-29Adds --log-commits commandline option. (#323)dave-estes-syzexion1-0/+3
* Adds --log-commits commandline option. Similar to histogram support, the commit logging feature must be enabled with a configure option: --enable-commitlog. However, unlike that feature, there was no way to turn off the logging with a commandline option once the functionality was built in. This (git) commit provides that abilty. * Changes addressing review feedback.
2019-09-05rvv: change vext to vmvChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-09-05Revert "vext.x.v -> vmv.x.s; unary operation encoding changes"Chih-Min Chao1-1/+1
This reverts commit f36b73e4741e42bf5786cbac0bf022f1e9bfe309. to makeh 0.7.2-0616-draft
2019-09-04rvv: refine check logic to use string as inputChih-Min Chao1-2/+14
allow "any", "1905", "e27" Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-09-04rvv: exit when there is unsupported instructionsChih-Min Chao1-0/+11
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-09-04rvv: reimplement check-1905 as check-implChih-Min Chao1-2/+9
build with --enable-check-imple run with --check-impl=1905 (or 1905 or future release) Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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