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AgeCommit message (Expand)AuthorFilesLines
2019-09-04Implement MMIO device plugins.Aaron Jones1-3/+64
2019-09-04Fix c.fldsp/c.fsdsp disassembly bugAndrew Waterman1-2/+2
2019-09-04vext.x.v -> vmv.x.s; unary operation encoding changesAndrew Waterman1-1/+1
2019-09-04vmfirst/vmpopc have been renamed to vfirst/vpopcAndrew Waterman1-2/+2
2019-08-02rvv: add vector-mistrp optionChih-Min Chao1-2/+2
2019-06-13rvv: separte vfunary0 into independent instructionsChih-Min Chao1-15/+16
2019-06-13rvv: spearate vfunary1 into independent instructionsChih-Min Chao1-4/+2
2019-06-09rvv: fix indentChih-Min Chao1-37/+37
2019-06-06rvv: follow new instruction name changeChih-Min Chao1-6/+6
2019-06-04rvv: sepapate vfmergeChih-Min Chao1-1/+2
2019-06-04rvv: move vadc/vsbc.v[vxi] to vadc/vsbc.v[vxi]mChih-Min Chao1-5/+21
2019-06-04rvv: separate vmerge and vmvChih-Min Chao1-1/+12
2019-06-04rvv: vmiota_m -> viota_mChih-Min Chao1-1/+1
2019-06-04rvv: change vseq.?? to vmseq.?? and related insnsChih-Min Chao1-8/+8
2019-06-04rvv: add vfrsub.vfChih-Min Chao1-0/+1
2019-06-04rvv: change vfeq to vmfeq and related comparision instructionChih-Min Chao1-7/+7
2019-05-29rvv: disasm: remove unused includeChih-Min Chao1-1/+0
2019-05-29Clean up debug module options. (#299)Tim Newsome1-25/+31
2019-05-29rvv: disas: add fault-first instructionsChih-Min Chao1-14/+30
2019-05-27rvv: disasm: shift should use unsiged viChih-Min Chao1-6/+6
2019-05-23rvv: fix rgatherChih-Min Chao1-1/+1
2019-05-22rvv: fix compressChih-Min Chao1-1/+1
2019-05-21rvv: disasm: fix vmsbf/sof/sif/vid operandChih-Min Chao1-4/+4
2019-05-20rvv: change viota_m to vmiota_mChih-Min Chao1-1/+1
2019-05-20rvv: add --check-1905 option to turn on 1905 release checkChih-Min Chao1-0/+5
2019-05-19rvv: separate vmuary0 by new encoding changeChih-Min Chao1-10/+7
2019-05-16rvv: fix integer reduction instruction suffixChih-Min Chao1-8/+8
2019-05-16rvv: disas: fix seg ld/st suffixChih-Min Chao1-35/+35
2019-05-16rvv: disas: fix segment load/storeChih-Min Chao1-52/+51
2019-05-14Add --debug-no-abstract-csr (#267)Tim Newsome1-1/+5
2019-05-14Implement debug hasel support (#287)Tim Newsome1-1/+5
2019-05-14Version 1.0.0Andrew Waterman1-0/+2
2019-05-14Add fesvr; only globally install fesvr headers/libsAndrew Waterman1-0/+1
2019-05-14Make --help return 0 after printing the help messageAndrew Waterman1-4/+11
2019-05-13Revert "Add FLH and FSH instructions expanding IEEE fp16 in memory to fp32 in...Chih-Min Chao1-2/+0
2019-05-10rvv: disasm: firx vfunary1 maskChih-Min Chao1-4/+4
2019-05-09Add a tool "spike-log-parser" to get the instruction name from spike log.Jerry Shih2-0/+61
2019-04-30rvv: spike-dasm doens't support configurable vector yet.Dave.Wen1-1/+1
2019-04-30rvv: configurable vector architecture during configuration andDave.Wen1-1/+4
2019-04-29rvv: disasm: fix vmunary0Chih-Min Chao1-10/+10
2019-04-28rvv: disasm: fix vfcvtChih-Min Chao1-5/+5
2019-04-24rvv: fix sign-injection namingChih-Min Chao1-2/+2
2019-04-24rvv: disas: add vmunary0Chih-Min Chao1-0/+10
2019-04-24rvv: disas: add vfunary0/1Chih-Min Chao1-2/+26
2019-04-24rvv: disas: use existing macroChih-Min Chao1-4/+2
2019-04-24rvv: disas: use correct macro prefixChih-Min Chao1-176/+176
2019-04-24rvv: disas: use existing macroChih-Min Chao1-11/+5
2019-04-19rvv: disasm: floating instruction use fregChih-Min Chao1-5/+5
2019-04-18disasm: add vsetvl disasm supportDave1-0/+1
2019-04-17disasm: handle most of vector alu instructionChih-Min Chao1-52/+267
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