aboutsummaryrefslogtreecommitdiff
path: root/spike_main
AgeCommit message (Expand)AuthorFilesLines
2020-04-16rvv: fix rtz cvtChih-Min Chao1-2/+2
2020-04-14rvv: disasm: leave only SEW-bit segment load/storeChih-Min Chao1-66/+0
2020-04-14rvv: add vfslide1[down|up].vf and refine checking ruleChih-Min Chao1-0/+2
2020-04-14rvv: add float conversion for rtz variantsChih-Min Chao1-1/+7
2020-04-14Handle misaligned memories by aligning them, rather than erroringAndrew Waterman1-1/+16
2020-04-14Revert "rvv: support simulations with mem size <4K"Chih-Min Chao1-1/+1
2020-04-07rvv: support simulations with mem size <4KDave.Wen1-1/+1
2020-04-05Write execution logs to a named log file (#409)Rupert Swarbrick2-5/+8
2020-03-04rvv: remove the option of vector misaligned accessZhen Wei1-3/+0
2020-03-04rvv: remove the option of vector impl. checkZhen Wei1-32/+0
2020-02-19Add optional support for real-time clintAnup Patel1-1/+5
2020-02-19Make spike capable of booting LinuxAnup Patel1-1/+39
2020-02-12Fix immediate signedness in vector disassemblyAndrew Waterman1-3/+3
2020-02-12Decouple spike-dasm program from simulator codeAndrew Waterman1-4/+21
2020-01-06rvv : vmv[1248]r.vChih-Min Chao1-4/+9
2019-12-12rvv: fix vfwcvt/vfncvt for f32 -> f64 and f64 -> f32Chih-Min Chao1-11/+9
2019-11-27rvv: add whole register load/store, vl1r.v/vs1r.vChih-Min Chao1-11/+11
2019-11-27rvv: replace vn suffic by 'w'Chih-Min Chao1-26/+30
2019-11-27rvv: add load/store whole registerChih-Min Chao1-0/+4
2019-11-27rvv: rename vfncvt suffix and add rod rouding typeChih-Min Chao1-15/+21
2019-11-27rvv: add quad insn and new vlenb csrChih-Min Chao1-5/+5
2019-11-17add vaaddu/vasubu/vfncvt.rod.f.f.v to diassemblerAndrew Waterman1-2/+5
2019-11-17Add --priv option to control which privilege modes are availableAndrew Waterman3-3/+6
2019-10-22rvv: remove vmfordChih-Min Chao1-1/+0
2019-10-14rvv: update encoding to v0.8Chih-Min Chao1-1/+1
2019-10-08Speed up compilation of disasm.cc, especially in clangAndrew Waterman1-1/+1
2019-09-29Adds --log-commits commandline option. (#323)dave-estes-syzexion1-0/+3
2019-09-05rvv: change vext to vmvChih-Min Chao1-1/+1
2019-09-05Revert "vext.x.v -> vmv.x.s; unary operation encoding changes"Chih-Min Chao1-1/+1
2019-09-04rvv: refine check logic to use string as inputChih-Min Chao1-2/+14
2019-09-04rvv: exit when there is unsupported instructionsChih-Min Chao1-0/+11
2019-09-04rvv: reimplement check-1905 as check-implChih-Min Chao1-2/+9
2019-09-04Implement MMIO device plugins.Aaron Jones1-3/+64
2019-09-04Fix c.fldsp/c.fsdsp disassembly bugAndrew Waterman1-2/+2
2019-09-04vext.x.v -> vmv.x.s; unary operation encoding changesAndrew Waterman1-1/+1
2019-09-04vmfirst/vmpopc have been renamed to vfirst/vpopcAndrew Waterman1-2/+2
2019-08-02rvv: add vector-mistrp optionChih-Min Chao1-2/+2
2019-06-13rvv: separte vfunary0 into independent instructionsChih-Min Chao1-15/+16
2019-06-13rvv: spearate vfunary1 into independent instructionsChih-Min Chao1-4/+2
2019-06-09rvv: fix indentChih-Min Chao1-37/+37
2019-06-06rvv: follow new instruction name changeChih-Min Chao1-6/+6
2019-06-04rvv: sepapate vfmergeChih-Min Chao1-1/+2
2019-06-04rvv: move vadc/vsbc.v[vxi] to vadc/vsbc.v[vxi]mChih-Min Chao1-5/+21
2019-06-04rvv: separate vmerge and vmvChih-Min Chao1-1/+12
2019-06-04rvv: vmiota_m -> viota_mChih-Min Chao1-1/+1
2019-06-04rvv: change vseq.?? to vmseq.?? and related insnsChih-Min Chao1-8/+8
2019-06-04rvv: add vfrsub.vfChih-Min Chao1-0/+1
2019-06-04rvv: change vfeq to vmfeq and related comparision instructionChih-Min Chao1-7/+7
2019-05-29rvv: disasm: remove unused includeChih-Min Chao1-1/+0
2019-05-29Clean up debug module options. (#299)Tim Newsome1-25/+31