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https://github.com/riscv/riscv-v-spec/commit/83fc27897b7b1fbc68e2e9e94f2ee05766315bac
https://github.com/riscv/riscv-v-spec/commit/fb40ef10f068827f3f0a926a83dd38ebcd470085
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* Don't corrupt s0 when abstract CSR write fails.
* Support abstract FPR access then mstatus.FS=0
Discussion on the spec list leans towards this being a requirement.
Certainly users want their debugger to be able to access all registers
regardless of target state.
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Fix DRET in M-mode, and change how D-mode is represented
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Resolves #308
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In the previous scheme, debug-mode software could exit debug mode by
zeroing the dcsr.cause field. While benign, that behavior is out of
spec.
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The subsequent for-loop provides sufficient initialization if we no
longer conditionalize its execution on vl being nonzero.
Resolves #307
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the tool can parse the instruction name from spike debug log to help
dsp kernel designer check what instructions have been used
Signed-off-by: Jerry Shih <bignose1007@gmail.com>
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based on v-spec 0.7.1, support
sections: 14/15.3 ~ 15.4
element size: 32
Signed-off-by: Bruce Hoult <bruce@hoult.org>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Dave Wen <dave.wen@sifive.com>
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based on v-spec 0.7.1, support
section: 7
element size: 8/16/32/64
Signed-off-by: Bruce Hoult <bruce@hoult.org>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Dave Wen <dave.wen@sifive.com>
Signed-off-by: Zakk Chen <zakk.chen@sifive.com>
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based on v-spec 0.7.1, support
sections: 12/13/15.1 ~ 15.2/16/17
element size: 8/16/32/64
support ediv: 1
Signed-off-by: Bruce Hoult <bruce@hoult.org>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Dave Wen <dave.wen@sifive.com>
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Signed-off-by: Bruce Hoult <bruce@hoult.org>
Signed-off-by: Dave Wen <dave.wen@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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1. add integer signed add/subu and unsigend add/sub saturation function
2. merge these with mulhi helper
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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add command to show vector register in debug mode
Signed-off-by: Bruce Hoult <bruce@hoult.org>
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the default vector parameters are defined in configuration time but can
be changed throught command-line option
Signed-off-by: Dave Wen <dave.wen@sifive.com>
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Signed-off-by: Bruce Hoult <bruce@hoult.org>
Signed-off-by: Dave Wen <dave.wen@sifive.com>
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1. configure option "--with-varch"
the option defines the default u-arch implementatiton-decided parameter
VLEN: vector register length in bit
SLEN: striping distance in bit
ELEN: max element size in bit
ex: --with-vector=v128:e32:s128
2. add __int128_t type checking
3. add --varch command option and help message
ex: --varch=v512:e64:s512
Signed-off-by: Dave Wen <dave.wen@sifive.com>
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support most of vector instruction except for AMO extension
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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It is a preparatory commit.
vector extension has supported segment load/store which have
the same prefix and a serial number as suffix.
ex:
base :
vlsegb.v
variation:
vlseg2.v, vlseg3b ... vlseg8b
dynamic string can reduce the typing effort
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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also remove duplicated one in fesvr
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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It is preparatory commit for vector extension.
v-ext has hundresds of new instructions and mixing them with scalar instructions
messes up code.
Separate each extension into different list to make thing clean
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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* Clean up debug module options.
1. Instead of passing each one a few levels deep, create
debug_module_config_t which contains them all.
2. Rename all those command line options so they start with --dm for
debug module.
3. Add --dm-no-halt-groups to disable halt group support.
* Update changelog.
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This is used to make sure that OpenOCD can work on targets that don't
support abstract access to CSR registers. It replaces a simpler hack,
which caused #266.
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* Implement hasel/hawindow support.
This should allow simultaneous resume and halt to work.
* Fix anyrunning/anyhalted bits.
* Add --without-hasel argument for testing.
* Make halt/resume times more equal.
Switching threads after every instruction executed in debug mode leads
to a lot of extra instructions being executed on the "other" thread when
both are really supposed to halt/resume near-simultaneously. Fixed that
by adding wfi to debug_rom.S, and implementing it to switch to the other
hart as well as check for JTAG input.
When resuming, write the hart ID to the debug ROM so that the DM knows
which hart actually resumed. (Before simultaneous resume it just assumed
the current one.)
Also got rid of resume symbol in debug_rom.S since it had no purpose.
* Preserve Debug ROM entry points.
* Make sure minstret is correct when wfi happens.
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https://github.com/riscv/riscv-isa-manual/commit/013ba6dc8a504ee4ad7bee42554fecaef7ba797f#diff-2a8fece1cbcdf623cafbce866ea7d4d0R7
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The spec says that e.g. MEI takes priority over SEI. We got this right in
the common case that SEI is delegated to S-mode, but we reversed it in the
undelegated case.
The destination privilege was correct, so this wasn't much of a problem,
but it is technically noncompliant.
Resolves #288
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This fixes the build on Alpine Linux (which uses musl libc).
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* Update debug_defines from latest spec.
* Implement halt groups.
This lets the debugger halt multiple harts near simultaneously.
* Revert encoding, which I updated accidentally.
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ee6fe6501a21ea8d167b6a5048527ba9eb924878 didn't get this right,
as it failed to add the offset to the address when checking each
4-byte sector of the access against hte PMPs.
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PMP checks should unconditionally fail if the PMP matches part of, but
not all of, an access. We got this right, but went too far: we checked
whether _any_ PMP matches in this manner. In fact, only the first PMP
that maches any of the bytes should be checked in this manner.
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Add --dmi-rti and --abstract-rti to test OpenOCD.
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This was a post-v1.10 amendment to the privileged spec.
https://github.com/riscv/riscv-isa-manual/commit/059f64c941856f249d8a0647e23e150dbdb1f62c
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This prevents duplicate I/Os to buffered streams early in the program.
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Optionally make spike behave more like real hardware, to automatically
test OpenOCD's handling of such hardware.
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Now we do what the spec says we should do. This ended up not having any
effect on the current way OpenOCD performs system bus accesses.
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Previously, the exception would only be raised if the store-conditional
would have succeeded.
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This is useful for example when the trace until a PC value needs
to be extracted (#246)
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https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md
TODO: allow Spike users to override marchid/mvendorid/mimpid to
mimic their hardware implementations more closely.
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* Add "--log-cache-miss" option to generate a log of cache miss.
- This option must be used with "--ic" and/or "--dc" options
to enable cache simulation.
- This option is useful with "-l" option to understand
which instruction has caused the cache miss.
* Modify log format of cache miss to reduce log size.
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