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2019-07-19vext.x.v -> vmv.x.s; unary operation encoding changesAndrew Waterman4-44/+39
https://github.com/riscv/riscv-v-spec/commit/83fc27897b7b1fbc68e2e9e94f2ee05766315bac https://github.com/riscv/riscv-v-spec/commit/fb40ef10f068827f3f0a926a83dd38ebcd470085
2019-07-16Writing non-existent CSRs, access FPRs with mstatus.FS=0 (#311)Tim Newsome5-7/+47
* Don't corrupt s0 when abstract CSR write fails. * Support abstract FPR access then mstatus.FS=0 Discussion on the spec list leans towards this being a requirement. Certainly users want their debugger to be able to access all registers regardless of target state.
2019-07-12Merge pull request #309 from riscv/dretAndrew Waterman5-12/+15
Fix DRET in M-mode, and change how D-mode is represented
2019-07-12Remove old header from makefileAndrew Waterman1-1/+0
Resolves #308
2019-07-12DRET should not be legal in M-modeAndrew Waterman1-1/+1
2019-07-12Add debug_mode state bit, rather than overloading dcsr.causeAndrew Waterman5-11/+14
In the previous scheme, debug-mode software could exit debug mode by zeroing the dcsr.cause field. While benign, that behavior is out of spec.
2019-07-11Fix support for 32-bit hosts (but no V extension in that case!)Andrew Waterman3-2/+9
2019-07-11Fix some 32-bit safety issuesAndrew Waterman2-3/+3
2019-07-11Support S-mode vectored interruptsAndrew Waterman1-2/+3
2019-07-05vmfirst/vmpopc have been renamed to vfirst/vpopcAndrew Waterman4-34/+45
2019-07-05Avoid static initializers for variable-length arraysAndrew Waterman1-2/+2
The subsequent for-loop provides sufficient initialization if we no longer conditionalize its execution on vl being nonzero. Resolves #307
2019-07-05Fix clang uninitialized variable warningAndrew Waterman1-1/+1
2019-06-18rvv: add simple instruction parsing toolChih-Min Chao1-1/+9
the tool can parse the instruction name from spike debug log to help dsp kernel designer check what instructions have been used Signed-off-by: Jerry Shih <bignose1007@gmail.com>
2019-06-18rvv: add floating-point instructionsChih-Min Chao83-1/+869
based on v-spec 0.7.1, support sections: 14/15.3 ~ 15.4 element size: 32 Signed-off-by: Bruce Hoult <bruce@hoult.org> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Dave Wen <dave.wen@sifive.com>
2019-06-18rvv: add load/store instructionsChih-Min Chao46-0/+569
based on v-spec 0.7.1, support section: 7 element size: 8/16/32/64 Signed-off-by: Bruce Hoult <bruce@hoult.org> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Dave Wen <dave.wen@sifive.com> Signed-off-by: Zakk Chen <zakk.chen@sifive.com>
2019-06-18rvv: add integer/fixed-point/mask/reduction/permutation instructionsChih-Min Chao217-0/+3473
based on v-spec 0.7.1, support sections: 12/13/15.1 ~ 15.2/16/17 element size: 8/16/32/64 support ediv: 1 Signed-off-by: Bruce Hoult <bruce@hoult.org> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Dave Wen <dave.wen@sifive.com>
2019-06-18rvv: add control instructions and system register accessChih-Min Chao5-0/+42
Signed-off-by: Bruce Hoult <bruce@hoult.org> Signed-off-by: Dave Wen <dave.wen@sifive.com> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-06-18rvv: add saturation helper functionChih-Min Chao3-44/+112
1. add integer signed add/subu and unsigend add/sub saturation function 2. merge these with mulhi helper Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-06-18rvv: extend interactive debugChih-Min Chao3-1/+51
add command to show vector register in debug mode Signed-off-by: Bruce Hoult <bruce@hoult.org>
2019-06-14rvv: add varch option parser and initialize vector unitChih-Min Chao4-11/+76
the default vector parameters are defined in configuration time but can be changed throught command-line option Signed-off-by: Dave Wen <dave.wen@sifive.com>
2019-06-14rvv: add vector unit structureChih-Min Chao2-0/+144
Signed-off-by: Bruce Hoult <bruce@hoult.org> Signed-off-by: Dave Wen <dave.wen@sifive.com>
2019-06-14rvv: add configuration and command-line optionChih-Min Chao1-0/+7
1. configure option "--with-varch" the option defines the default u-arch implementatiton-decided parameter VLEN: vector register length in bit SLEN: striping distance in bit ELEN: max element size in bit ex: --with-vector=v128:e32:s128 2. add __int128_t type checking 3. add --varch command option and help message ex: --varch=v512:e64:s512 Signed-off-by: Dave Wen <dave.wen@sifive.com>
2019-06-14rvv: disasm: add v-spec 0.7.1 supportChih-Min Chao3-3/+39
support most of vector instruction except for AMO extension Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-06-14disams: make instruction name dynamicChih-Min Chao1-1/+2
It is a preparatory commit. vector extension has supported segment load/store which have the same prefix and a serial number as suffix. ex: base : vlsegb.v variation: vlseg2.v, vlseg3b ... vlseg8b dynamic string can reduce the typing effort Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-06-14rvv: add the v-spec-0.7.1 encodingChih-Min Chao1-11/+1218
also remove duplicated one in fesvr Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-06-09rvv: re-arrange instruction list by different extensionChih-Min Chao1-129/+155
It is preparatory commit for vector extension. v-ext has hundresds of new instructions and mixing them with scalar instructions messes up code. Separate each extension into different list to make thing clean Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-05-14Clean up debug module options. (#299)Tim Newsome4-60/+49
* Clean up debug module options. 1. Instead of passing each one a few levels deep, create debug_module_config_t which contains them all. 2. Rename all those command line options so they start with --dm for debug module. 3. Add --dm-no-halt-groups to disable halt group support. * Update changelog.
2019-04-04Add --debug-no-abstract-csr (#267)Tim Newsome4-11/+12
This is used to make sure that OpenOCD can work on targets that don't support abstract access to CSR registers. It replaces a simpler hack, which caused #266.
2019-04-02Implement debug hasel support (#287)Tim Newsome6-72/+138
* Implement hasel/hawindow support. This should allow simultaneous resume and halt to work. * Fix anyrunning/anyhalted bits. * Add --without-hasel argument for testing. * Make halt/resume times more equal. Switching threads after every instruction executed in debug mode leads to a lot of extra instructions being executed on the "other" thread when both are really supposed to halt/resume near-simultaneously. Fixed that by adding wfi to debug_rom.S, and implementing it to switch to the other hart as well as check for JTAG input. When resuming, write the hart ID to the debug ROM so that the DM knows which hart actually resumed. (Before simultaneous resume it just assumed the current one.) Also got rid of resume symbol in debug_rom.S since it had no purpose. * Preserve Debug ROM entry points. * Make sure minstret is correct when wfi happens.
2019-03-31Add fesvr; only globally install fesvr headers/libsstatic-linkAndrew Waterman1-11/+0
2019-03-30RV32Q is not invalidAndrew Waterman1-3/+0
https://github.com/riscv/riscv-isa-manual/commit/013ba6dc8a504ee4ad7bee42554fecaef7ba797f#diff-2a8fece1cbcdf623cafbce866ea7d4d0R7
2019-03-27Respect interrupt priorities even when not delegatedAndrew Waterman1-9/+13
The spec says that e.g. MEI takes priority over SEI. We got this right in the common case that SEI is delegated to S-mode, but we reversed it in the undelegated case. The destination privilege was correct, so this wasn't much of a problem, but it is technically noncompliant. Resolves #288
2019-03-12include sys/types.h for suseconds_t (#285)nmeum1-0/+1
This fixes the build on Alpine Linux (which uses musl libc).
2019-03-04Implement halt groups (#280)Tim Newsome3-176/+649
* Update debug_defines from latest spec. * Implement halt groups. This lets the debugger halt multiple harts near simultaneously. * Revert encoding, which I updated accidentally.
2019-02-28Further fix PMP checks for partially-matching accesses (#270)Andrew Waterman1-3/+4
ee6fe6501a21ea8d167b6a5048527ba9eb924878 didn't get this right, as it failed to add the offset to the address when checking each 4-byte sector of the access against hte PMPs.
2019-02-04Fix use of old name `riscv-isa-run` (#269)Luís Marques1-1/+1
2019-02-04fixing compilation errors on openbsdDinesh Thirumurthy1-0/+7
2019-01-28Fix PMP checks for partially-matching accesses (#270)Andrew Waterman2-8/+21
PMP checks should unconditionally fail if the PMP matches part of, but not all of, an access. We got this right, but went too far: we checked whether _any_ PMP matches in this manner. In fact, only the first PMP that maches any of the bytes should be checked in this manner.
2019-01-09Merge pull request #265 from riscv/debug_testTim Newsome6-36/+84
Add --dmi-rti and --abstract-rti to test OpenOCD.
2018-12-21Reserve the PMP R=0 W=1 combinationAndrew Waterman1-2/+5
This was a post-v1.10 amendment to the privileged spec. https://github.com/riscv/riscv-isa-manual/commit/059f64c941856f249d8a0647e23e150dbdb1f62c
2018-12-19Flush I/O buffers before forkingAndrew Waterman1-0/+1
This prevents duplicate I/Os to buffered streams early in the program.
2018-12-13Add --dmi-rti and --abstract-rti to test OpenOCD.Tim Newsome6-36/+84
Optionally make spike behave more like real hardware, to automatically test OpenOCD's handling of such hardware.
2018-12-03Correct address autoincrement calls. (#263)Tim Newsome1-2/+5
Now we do what the spec says we should do. This ended up not having any effect on the current way OpenOCD performs system bus accesses.
2018-11-06Report misaligned-address exception on failed store-conditionalsAndrew Waterman2-14/+8
Previously, the exception would only be raised if the store-conditional would have succeeded.
2018-10-18Provide a noisy until interactive commandHesham Almatary2-6/+20
This is useful for example when the trace until a PC value needs to be extracted (#246)
2018-10-04Set marchid to assigned value 5Andrew Waterman1-1/+1
https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md TODO: allow Spike users to override marchid/mvendorid/mimpid to mimic their hardware implementations more closely.
2018-09-27Add comment about CSR read side effectsAndrew Waterman1-0/+3
2018-09-25For backwards compatibility, reset PMP to permit all accessesAndrew Waterman1-0/+3
2018-09-25Add PMP supportAndrew Waterman4-24/+147
2018-09-24Add "--log-cache-miss" option to generate a log of cache miss. (#241)takeoverjp2-2/+14
* Add "--log-cache-miss" option to generate a log of cache miss. - This option must be used with "--ic" and/or "--dc" options to enable cache simulation. - This option is useful with "-l" option to understand which instruction has caused the cache miss. * Modify log format of cache miss to reduce log size.
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