aboutsummaryrefslogtreecommitdiff
path: root/riscv
AgeCommit message (Expand)AuthorFilesLines
2019-11-15Re-encode vaadd/vasub; remove vaadd.vi; add vaaddu/vasubuAndrew Waterman2-44/+55
2019-11-12mstatus.FS only exists if (S || V || F)Andrew Waterman1-1/+5
2019-11-12Remove S-mode interrupts when S-mode not presentAndrew Waterman1-5/+12
2019-11-12Fix mode-transition logic when S-mode not presentAndrew Waterman1-1/+1
2019-11-12SRET requires S-modeAndrew Waterman1-0/+1
2019-11-12Remove S-mode CSRs when S-mode is not presentAndrew Waterman1-1/+2
2019-11-12Add --priv option to control which privilege modes are availableAndrew Waterman5-10/+44
2019-11-12Factor out boilerplate strtolower functionAndrew Waterman1-3/+9
2019-11-12In parse_isa_string, populate max_isa rather than state.misaAndrew Waterman1-7/+3
2019-11-11rvv: add 'V' ext check for each vector insnChih-Min Chao1-1/+1
2019-11-11rvv: fix reg checking for vmadc/vmsbcChih-Min Chao5-5/+0
2019-11-11rvv: add reg checking for specifial instructionsChih-Min Chao14-79/+51
2019-11-11rvv: add reg checking rule to vslide instructionsChih-Min Chao6-10/+37
2019-11-11rvv: add reg checking rule for ldstChih-Min Chao17-8/+32
2019-11-11rvv: add reg checking rule for general fomratChih-Min Chao18-5/+38
2019-11-11rvv: add reg checking rule for comparison instrucitonsChih-Min Chao11-11/+29
2019-11-11rvv: add reg checking rule for reductionChih-Min Chao1-5/+12
2019-11-11rvv: add register using check for wide and narrow insnChih-Min Chao19-51/+66
2019-11-11rvv: refine vsetvl[i] logicChih-Min Chao2-5/+18
2019-11-11rvv: fix vsmul sign and variable typeChih-Min Chao2-25/+23
2019-11-11rvv: fix vssr/vssra rounding issueChih-Min Chao6-12/+19
2019-11-11rvv: fix the rounding bit position for vnclip instructions.Albert Ou6-50/+34
2019-11-11rvv: fix INT_ROUNDING complianceAlbert Ou1-14/+10
2019-11-11rvv: remove configuable tail-zeroChih-Min Chao16-186/+41
2019-11-11rvv: fix redsum/vmv for non-tail-zero caseChih-Min Chao3-28/+27
2019-11-11rvv: fix vmv.x.s signed-ext issueChih-Min Chao2-23/+26
2019-10-29rvv: fix floating-point exception for comparisonChih-Min Chao6-5/+6
2019-10-29rvv: remove vmfordChih-Min Chao4-18/+0
2019-10-28Implement support for big-endian hostsMarcus Comstedt6-36/+84
2019-10-24Initialize histogram_enabled and log_commits_enabled in constructor (#354)Scott Johnson1-0/+1
2019-10-22Catch polymorphic exceptions by reference (#352)Luís Marques1-2/+2
2019-10-22Stop loading "past the end" of the vector. (#351)Nick Knight1-5/+5
2019-10-16Enforce 2^56-bit physical address limitAndrew Waterman2-2/+10
2019-10-07Speed up compilation of disasm.cc, especially in clangAndrew Waterman2-2/+4
2019-09-27Fixed match trigger MATCH_NAPOT case. (#335)fborisovskii1-1/+1
2019-09-18Extends the commit log feature with memory writes. (#324)dave-estes-syzexion3-6/+37
2019-09-18Adds --log-commits commandline option. (#323)dave-estes-syzexion5-2/+31
2019-08-28Merge pull request #315 from vexingcodes/mmio-pluginAndrew Waterman6-4/+158
2019-08-23Remove statement with no effectAndrew Waterman1-1/+0
2019-07-22Implement MMIO device plugins.Aaron Jones6-4/+158
2019-07-19Set vtype.vill correctly; also reset it to trueAndrew Waterman1-3/+8
2019-07-19Check presence of V extension when accessing vector CSRsAndrew Waterman1-0/+15
2019-07-19Check vtype.vill for all vector instructions except vsetvl[i]Andrew Waterman24-20/+37
2019-07-19VL and VTYPE aren't writable CSRsAndrew Waterman1-12/+0
2019-07-19Check for F extension in vfmv instructionsAndrew Waterman2-0/+2
2019-07-19Avoid relying on sizeof longAndrew Waterman3-5/+5
2019-07-19vext.x.v -> vmv.x.s; unary operation encoding changesAndrew Waterman4-44/+39
2019-07-16Writing non-existent CSRs, access FPRs with mstatus.FS=0 (#311)Tim Newsome5-7/+47
2019-07-12Merge pull request #309 from riscv/dretAndrew Waterman5-12/+15
2019-07-12Remove old header from makefileAndrew Waterman1-1/+0