index
:
rocket-tools/riscv-gnu-toolchain/spike.git
confprec
cs250
cycleh
debug_rom
debug_rom_fence
device_flags
dtm_reset_error
dts_parsing
dynamic
eos18-bringup
factor-out-macros
fix-bf16
force-rtti
fp-encoding
heterogeneous_mc
hwachav4
increase-stack-size
itrigger-etrigger-cleanup
load_reservation_set_size
log-commits-faster
master
mmio-hack
mvp
no_progbuf
no_progbuf2
nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
plic-clint-endian
plic_uart_v1
priv-1.10
private-l1-caches
pte-info-and-delegation
remove-tests
rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
sparse-mem
speedup-hacks
static-link
test
tmp
trigger_priority
tweak_debug_rom
whole-archive
sifive/rvv0.9-phase2
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
riscv
Age
Commit message (
Expand
)
Author
Files
Lines
2019-11-12
mstatus.FS only exists if (S || V || F)
Andrew Waterman
1
-1
/
+5
2019-11-12
Remove S-mode interrupts when S-mode not present
Andrew Waterman
1
-5
/
+12
2019-11-12
Fix mode-transition logic when S-mode not present
Andrew Waterman
1
-1
/
+1
2019-11-12
SRET requires S-mode
Andrew Waterman
1
-0
/
+1
2019-11-12
Remove S-mode CSRs when S-mode is not present
Andrew Waterman
1
-1
/
+2
2019-11-12
Add --priv option to control which privilege modes are available
Andrew Waterman
5
-10
/
+44
2019-11-12
Factor out boilerplate strtolower function
Andrew Waterman
1
-3
/
+9
2019-11-12
In parse_isa_string, populate max_isa rather than state.misa
Andrew Waterman
1
-7
/
+3
2019-11-11
rvv: add 'V' ext check for each vector insn
Chih-Min Chao
1
-1
/
+1
2019-11-11
rvv: fix reg checking for vmadc/vmsbc
Chih-Min Chao
5
-5
/
+0
2019-11-11
rvv: add reg checking for specifial instructions
Chih-Min Chao
14
-79
/
+51
2019-11-11
rvv: add reg checking rule to vslide instructions
Chih-Min Chao
6
-10
/
+37
2019-11-11
rvv: add reg checking rule for ldst
Chih-Min Chao
17
-8
/
+32
2019-11-11
rvv: add reg checking rule for general fomrat
Chih-Min Chao
18
-5
/
+38
2019-11-11
rvv: add reg checking rule for comparison instrucitons
Chih-Min Chao
11
-11
/
+29
2019-11-11
rvv: add reg checking rule for reduction
Chih-Min Chao
1
-5
/
+12
2019-11-11
rvv: add register using check for wide and narrow insn
Chih-Min Chao
19
-51
/
+66
2019-11-11
rvv: refine vsetvl[i] logic
Chih-Min Chao
2
-5
/
+18
2019-11-11
rvv: fix vsmul sign and variable type
Chih-Min Chao
2
-25
/
+23
2019-11-11
rvv: fix vssr/vssra rounding issue
Chih-Min Chao
6
-12
/
+19
2019-11-11
rvv: fix the rounding bit position for vnclip instructions.
Albert Ou
6
-50
/
+34
2019-11-11
rvv: fix INT_ROUNDING compliance
Albert Ou
1
-14
/
+10
2019-11-11
rvv: remove configuable tail-zero
Chih-Min Chao
16
-186
/
+41
2019-11-11
rvv: fix redsum/vmv for non-tail-zero case
Chih-Min Chao
3
-28
/
+27
2019-11-11
rvv: fix vmv.x.s signed-ext issue
Chih-Min Chao
2
-23
/
+26
2019-10-29
rvv: fix floating-point exception for comparison
Chih-Min Chao
6
-5
/
+6
2019-10-29
rvv: remove vmford
Chih-Min Chao
4
-18
/
+0
2019-10-28
Implement support for big-endian hosts
Marcus Comstedt
6
-36
/
+84
2019-10-24
Initialize histogram_enabled and log_commits_enabled in constructor (#354)
Scott Johnson
1
-0
/
+1
2019-10-22
Catch polymorphic exceptions by reference (#352)
Luís Marques
1
-2
/
+2
2019-10-22
Stop loading "past the end" of the vector. (#351)
Nick Knight
1
-5
/
+5
2019-10-16
Enforce 2^56-bit physical address limit
Andrew Waterman
2
-2
/
+10
2019-10-07
Speed up compilation of disasm.cc, especially in clang
Andrew Waterman
2
-2
/
+4
2019-09-27
Fixed match trigger MATCH_NAPOT case. (#335)
fborisovskii
1
-1
/
+1
2019-09-18
Extends the commit log feature with memory writes. (#324)
dave-estes-syzexion
3
-6
/
+37
2019-09-18
Adds --log-commits commandline option. (#323)
dave-estes-syzexion
5
-2
/
+31
2019-08-28
Merge pull request #315 from vexingcodes/mmio-plugin
Andrew Waterman
6
-4
/
+158
2019-08-23
Remove statement with no effect
Andrew Waterman
1
-1
/
+0
2019-07-22
Implement MMIO device plugins.
Aaron Jones
6
-4
/
+158
2019-07-19
Set vtype.vill correctly; also reset it to true
Andrew Waterman
1
-3
/
+8
2019-07-19
Check presence of V extension when accessing vector CSRs
Andrew Waterman
1
-0
/
+15
2019-07-19
Check vtype.vill for all vector instructions except vsetvl[i]
Andrew Waterman
24
-20
/
+37
2019-07-19
VL and VTYPE aren't writable CSRs
Andrew Waterman
1
-12
/
+0
2019-07-19
Check for F extension in vfmv instructions
Andrew Waterman
2
-0
/
+2
2019-07-19
Avoid relying on sizeof long
Andrew Waterman
3
-5
/
+5
2019-07-19
vext.x.v -> vmv.x.s; unary operation encoding changes
Andrew Waterman
4
-44
/
+39
2019-07-16
Writing non-existent CSRs, access FPRs with mstatus.FS=0 (#311)
Tim Newsome
5
-7
/
+47
2019-07-12
Merge pull request #309 from riscv/dret
Andrew Waterman
5
-12
/
+15
2019-07-12
Remove old header from makefile
Andrew Waterman
1
-1
/
+0
2019-07-12
DRET should not be legal in M-mode
Andrew Waterman
1
-1
/
+1
[next]