rocket-tools/riscv-gnu-toolchain/spike.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-04-27	rvv: commitlog: fix comparision dst information	Chih-Min Chao	3	-6/+9
2020-04-24	rvv: commitlog: fix missing informaiton for slide1	Chih-Min Chao	4	-12/+12
2020-04-24	rvv: commitlog: fix dst information for int comparison	Chih-Min Chao	1	-20/+40
2020-04-23	build: quota string with [] to avoid part of string missing	Chih-Min Chao	1	-1/+1
2020-04-23	rvv: fix vfncvt.xu.f.w for fp16	Chih-Min Chao	1	-1/+1
2020-04-23	rvv: aad fp16 support for vfwxxx.[wv]v	Chih-Min Chao	10	-8/+47
2020-04-22	rvv: fix segment load/store nf checking	Chih-Min Chao	2	-9/+11
2020-04-21	rvv: fix vfmv for fp16	Chih-Min Chao	3	-13/+36
2020-04-21	rvv: fix vfmerge.vfm for fp16	Chih-Min Chao	1	-2/+15
2020-04-21	rvv: fix vfslide for fp16	Chih-Min Chao	2	-0/+16
2020-04-21	rvv: fix floating comparison for fp16	Chih-Min Chao	10	-11/+49
2020-04-21	rvv: allow fp16	Chih-Min Chao	1	-1/+2
2020-04-20	rvv: refine vfncvt case for f32_to_[u]i16 cases	Chih-Min Chao	3	-6/+3
2020-04-20	rvv: fix f16_to_[u]i16 conversion	Chih-Min Chao	4	-8/+4
2020-04-20	rvv: remove debug message	Chih-Min Chao	1	-1/+0
2020-04-19	rvv: fix vfwredsum checking rule	Chih-Min Chao	1	-1/+3
2020-04-16	rvv: fix rtz cvt	Chih-Min Chao	13	-51/+47
2020-04-15	rvv: add widen conversion instructions	Chih-Min Chao	7	-51/+53
2020-04-15	rvv: add narrow conversion instrucitons	Chih-Min Chao	7	-42/+71
2020-04-15	rvv: add normal and widen reduction instructions	Chih-Min Chao	7	-27/+78
2020-04-15	rvv: add vmfxx f16 compare instructions	Chih-Min Chao	11	-2/+39
2020-04-15	rvv: add .vf fp16 instructions	Chih-Min Chao	25	-3/+85
2020-04-15	rvv: add .vv fp16 instructions	Chih-Min Chao	22	-2/+72
2020-04-15	rvv: WIDE_END loop macro	Chih-Min Chao	1	-9/+4
2020-04-15	fp16: add helper macro	Chih-Min Chao	1	-0/+8
2020-04-14	parser: extend --isa to support extended extension	Chih-Min Chao	2	-18/+55
2020-04-14	rvv: leave only SEW-bit segment store	Chih-Min Chao	17	-153/+53
2020-04-14	rvv: leave only sew-wise segment load	Chih-Min Chao	29	-73/+76
2020-04-14	rvv: add vfslide1[down\|up].vf and refine checking rule	Chih-Min Chao	11	-27/+79
2020-04-14	rvv: add float conversion for rtz variants	Chih-Min Chao	8	-0/+88
2020-04-14	rvv: add new vcsr vector csr	Chih-Min Chao	3	-19/+31
2020-04-10	rvv: remove unecessary initialization	Chih-Min Chao	1	-1/+0
2020-04-10	rvv: vslide[1]up now allows mask overlap when LMUL=1	Chih-Min Chao	3	-3/+3
2020-04-10	rvv: fix index segment load overlapping check	Chih-Min Chao	1	-5/+7
2020-04-10	op: update CSR	Chih-Min Chao	3	-12/+38
2020-04-10	rvv: missing vector enabling check for mask operation	Chih-Min Chao	1	-0/+1
2020-04-05	Fix debug segfault by partially reverting #409	Andrew Waterman	1	-2/+3
2020-04-05	option: flag x extension without loading shared lib (#439)	Chih-Min Chao	1	-1/+5
2020-04-05	Deny hart access to debug CSRs when not in D-mode	Andrew Waterman	1	-0/+8
2020-04-05	Assert that debug_module is initialized correctly. (#437)	Tim Newsome	1	-0/+1
2020-04-05	Write execution logs to a named log file (#409)	Rupert Swarbrick	6	-78/+144
2020-04-05	Allow PATH lookup for executing dtc (#432)	綺麗な賢狼ホロ	1	-1/+1
2020-04-05	Don't acquire load reservation in the event of a fault	Andrew Waterman	2	-2/+4
2020-04-05	ebreak should write mtval with 0, not pc	Andrew Waterman	3	-3/+3
2020-03-27	rvv: fix int_max/min value calculation	Chih-Min Chao	8	-23/+26
2020-03-26	rvv: fix vssraa.vi e64 corner case	Chih-Min Chao	1	-1/+1
2020-03-26	rvv: check vlen == slen	Chih-Min Chao	1	-0/+2
2020-03-24	rvv: fix vmv reg checking failure	Chih-Min Chao	3	-1/+6
2020-03-23	rvv: restrict segment load register rule	Chih-Min Chao	4	-3/+4
2020-03-23	rvv: fix WARL behavior for vxsat and vxrm	Chih-Min Chao	1	-2/+2