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AgeCommit message (Expand)AuthorFilesLines
2011-05-16[sim,pk] cleanups & initial virtual memory supportAndrew Waterman7-39/+70
2011-05-16[sim,xcc] change cond. mov inst format, add implementationYunsup Lee4-0/+8
2011-05-15[opcodes,pk,sim,xcc] resolve a conflictYunsup Lee1-4/+19
2011-05-15[libs,opcodes,pk,sim,xcc] add mov*,fmov*, shuffle vec instsYunsup Lee76-202/+212
2011-05-13[sim] initial support for virtual memoryAndrew Waterman3-18/+131
2011-05-13[sim] stubs for perfctr instructionsAndrew Waterman3-0/+3
2011-05-13tweaked encoding of rdcycle & cousinsAndrew Waterman1-23/+38
2011-05-06[sim] fixed building sim without cache simulatorsAndrew Waterman1-1/+1
2011-04-30[sim] hacked in a dcache simulatorAndrew Waterman8-43/+187
2011-04-24[xcc,sim,opcodes] added c.addiwAndrew Waterman2-3569/+559
2011-04-24[xcc,sim,opcodes] added more RVC instructionsAndrew Waterman22-12/+2642
2011-04-23[sim] fixed divw/remw crashing simulatorAndrew Waterman2-6/+2
2011-04-18[xcc,sim] rv64 'w' instruction semantics changedAndrew Waterman2-2/+2
2011-04-18[xcc,sim,opcodes] added rvc conditional branchesAndrew Waterman4-4/+53
2011-04-16[sim] removed undefined behavior for non-canonical inputsAndrew Waterman13-13/+15
2011-04-16[sim] added "str" debug commandAndrew Waterman2-0/+18
2011-04-15[sim] fixed jalr immediate bugAndrew Waterman1-2/+2
2011-04-15[sim] added icache simulator (disabled by default)Andrew Waterman11-7/+136
2011-04-12[xcc,pk,sim] added privileged cflush instructionAndrew Waterman2-0/+10
2011-04-12[xcc,sim] fixed RM fieldAndrew Waterman1-2/+4
2011-04-12[xcc,sim] rvc loads and storesAndrew Waterman10-1/+187
2011-04-12[sim,pk] fixed minor pk bugs and trap codesAndrew Waterman2-4/+7
2011-04-11[sim] fixed FSR exception field bugAndrew Waterman1-1/+1
2011-04-11[xcc,sim,opcodes] more rvc instructions and bug fixesAndrew Waterman8-6/+507
2011-04-09[sim] add disable option for vectorYunsup Lee2-0/+8
2011-04-09[sim] set SR_EV for utsYunsup Lee1-0/+1
2011-04-09[sim] add vector traps to vector instructionsYunsup Lee44-1/+44
2011-04-09[sim] add vt stuffYunsup Lee47-3/+189
2011-04-09[xcc, sim] added rvc insn c.li; misc fixesAndrew Waterman3-1/+26
2011-04-09[sim,pk] reorganized status registerAndrew Waterman4-13/+18
2011-04-09[xcc,pk,sim,opcodes] added first RVC instructionAndrew Waterman6-109/+125
2011-04-08[sim] fixed multiply-high in rv32Andrew Waterman2-2/+2
2011-04-07[pk,sim] fixed parse-opcodes bugAndrew Waterman1-0/+173
2011-04-06[opcodes,pk,sim,xcc] fix utidx - add rdYunsup Lee1-1/+1
2011-04-05[opcodes,pk,sim,xcc] fix vector mem instruction format, add vector seg mem in...Yunsup Lee37-50/+242
2011-04-04[opcodes,pk,sim,xcc] add leftover vector instructions (vf, etc.)Yunsup Lee6-0/+52
2011-04-04[opcodes,pk,sim,xcc] add vector mem instructionsYunsup Lee31-0/+208
2011-04-04[opcodes,pk,sim,xcc] add stop,utidx instructionsYunsup Lee3-0/+18
2011-04-04[opcodes,pk,sim,xcc] add fence instructions for vector unitYunsup Lee5-0/+20
2011-03-30[xcc] fixed bug in amo{maxu,minu}.wAndrew Waterman2-2/+2
2011-03-25[opcodes] minor opcode changesAndrew Waterman1-89/+100
2011-03-25[sim,pk,xcc,opcodes] removed fminmag/fmaxmagAndrew Waterman5-44/+0
2011-03-25[xcc,pk,opcodes,sim] updated encoding/insn namesAndrew Waterman16-143/+241
2011-03-17[sim] LWU now illegal in RV32Andrew Waterman1-0/+1
2011-03-01[xcc,sim] branches are pc-relative (not pc+4) againAndrew Waterman1-2/+2
2011-02-15[xcc,opcodes,pk,sim] krste's re-renaming spreeAndrew Waterman40-93/+93
2011-02-15[xcc,sim,opcodes] removed mtflh/mffl/mffhAndrew Waterman4-24/+0
2011-02-04[sim,pk] added interrupt-pending field to cause regAndrew Waterman5-13/+13
2011-02-02[sim,xcc,opcodes] added back mtflh.dAndrew Waterman3-5/+11
2011-02-02[opcodes,pk,sim,xcc] synci now bombs whole icacheAndrew Waterman1-9/+9
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