rocket-tools/riscv-gnu-toolchain/spike.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-03-27	Write execution logs to a named log file (#409)	Rupert Swarbrick	6	-78/+144
2020-03-24	Allow PATH lookup for executing dtc (#432)	綺麗な賢狼ホロ	1	-1/+1
2020-03-23	rvv: restrict segment load register rule	Chih-Min Chao	4	-3/+4
2020-03-23	rvv: fix WARL behavior for vxsat and vxrm	Chih-Min Chao	1	-2/+2
2020-03-23	rvv: fix vdiv corner case	Chih-Min Chao	2	-2/+2
2020-03-23	commitlog: fix wrong dump when exception occurs	Chih-Min Chao	2	-8/+15
2020-03-23	Don't acquire load reservation in the event of a fault	Andrew Waterman	2	-2/+4
2020-03-20	ebreak should write mtval with 0, not pc	Andrew Waterman	3	-3/+3
2020-03-12	rvv: commitlog: fix vrgather_vv dump (#421)	Chih-Min Chao	1	-4/+4
2020-03-12	rvv: commitlog: fix missing dump for some instructions	Chih-Min Chao	8	-29/+32
2020-03-12	rvv: fix vfmv.s.f and vfmv.f.s	Chih-Min Chao	2	-1/+3
2020-03-09	op: rvv: update encoding	Chih-Min Chao	1	-315/+372
2020-03-09	commitlog: enhance vector dump	Chih-Min Chao	2	-5/+17
2020-03-09	rvv: enhance --varch to parse string type options	Zhen Wei	2	-32/+44
2020-03-09	rvv: handle middle value of vslidedown.vx	Chih-Min Chao	1	-1/+1
2020-03-09	rvv: vstart must be 0 for reduction instructions	Chih-Min Chao	1	-0/+1
2020-03-05	Make debug printfs only show in debug builds. (#414)	Andrew Waterman	1	-6/+6
2020-03-04	Don't clobber trigger types when initializing state	Andrew Waterman	1	-1/+1
2020-02-28	Add do-nothing support for mcountinhibit CSR	Rupert Swarbrick	2	-0/+3
2020-02-27	Merge pull request #405 from riscv/mstatus-sxl-uxl	Udit Khanna	1	-7/+8
2020-02-27	Check presence of [S\|U] extension for mstatus.[sxl\|uxl] read/write	Udit Khanna	1	-7/+8
2020-02-21	Allow debug accesses from MMUs not bound to processors	Andrew Waterman	1	-1/+1
2020-02-21	Initialize some uninitialized state	Andrew Waterman	2	-1/+4
2020-02-20	Disallow access to debug memory region unless in debug mode	Andrew Waterman	2	-3/+31
2020-02-20	Debug can actually start at 0x0 now	Andrew Waterman	1	-2/+1
2020-02-20	rvv: only check segment overlapping in index load	Chih-Min Chao	1	-4/+2
2020-02-20	rvv: also relax vmerge_vim/vvm when lmul = 1	Chih-Min Chao	2	-2/+0
2020-02-20	rvv: also relax lmul in vfwredum	Chih-Min Chao	2	-2/+0
2020-02-20	commitlog: print vsew in bit	Chih-Min Chao	1	-1/+1
2020-02-20	rvv: don't zero vstart in the beginning	Chih-Min Chao	1	-1/+0
2020-02-18	widening reductions are legal when LMUL=8	Andrew Waterman	1	-1/+0
2020-02-18	Vector stores don't care if rd overlaps v0 (#400)	Andrew Waterman	5	-13/+20
2020-02-18	Merge pull request #396 from chihminchao/rvv-fix-2020-02-14	Andrew Waterman	17	-25/+31
2020-02-18	commitlog: fix printf format warning	Chih-Min Chao	1	-1/+1
2020-02-18	rvv: make variable name match its meaning	Chih-Min Chao	4	-4/+4
2020-02-18	rvv: fix vmsleu/vmsgtu/vsaddu.vi operand signed extension	Chih-Min Chao	3	-3/+3
2020-02-17	v[f]merge: allow v0 overlap if LMUL = 1	Andrew Waterman	2	-2/+0
2020-02-17	vadc/vsbc: allow v0 overlap if LMUL = 1	Andrew Waterman	1	-2/+2
2020-02-15	Make CLINT API use Hz instead of MHz	Andrew Waterman	3	-6/+6
2020-02-15	Add optional support for real-time clint	Anup Patel	4	-7/+30
2020-02-14	rvv: fix exception rethrow in fault-first load	Chih-Min Chao	1	-1/+1
2020-02-14	rvv: reset vstart to 0 when vmv.s.x and vmv.x.s and also check the vstart < v...	Dave.Wen	2	-1/+5
2020-02-14	rvv: respect vstart in fault-first load	Chih-Min Chao	1	-3/+3
2020-02-14	rvv: vms[bio]f.m need to start from 0	Chih-Min Chao	3	-6/+3
2020-02-14	rvv: vsbc/vmsbc behavior of the sub order	Max Lin	4	-4/+4
2020-02-14	rvv: fix Vxrm not reflected in fcsr	Dave.Wen	1	-2/+7
2020-02-14	Make spike capable of booting Linux	Anup Patel	4	-4/+17
2020-02-12	Improve --varch error checking. (#394)	Tim Newsome	2	-10/+20
2020-02-06	Fix incorrect comments	Andrew Waterman	2	-2/+2
2020-01-30	Fix pmpcfg0 initial value regression from cb254bfab5fbb6d69e5dd336798861e7c11...	Andrew Waterman	1	-5/+5