aboutsummaryrefslogtreecommitdiff
path: root/riscv
AgeCommit message (Expand)AuthorFilesLines
2015-03-30Implement RVC draftAndrew Waterman26-440/+593
2015-03-26Serialize counters without throwing C++ exceptionsAndrew Waterman3-22/+27
2015-03-26New virtual memory implementation (Sv39)Andrew Waterman3-63/+79
2015-03-25Update state.pc on every instructionAndrew Waterman1-4/+3
2015-03-20For misaligned fetch, set mepc = addr of branch/jumpAndrew Waterman1-1/+5
2015-03-17bugfix, mbadaddr should be writableYunsup Lee1-0/+1
2015-03-17Merge [shm]call into ecall, [shm]ret into eretAndrew Waterman7-38/+24
2015-03-16bugfix in raising accelerator interruptsYunsup Lee1-1/+8
2015-03-14Don't set dirty/referenced bits w/o permissionAndrew Waterman2-15/+16
2015-03-12Use hcall instead of mcallAndrew Waterman4-8/+13
2015-03-12Implement PTE referenced/dirty bitsAndrew Waterman3-14/+16
2015-03-12Update to new privileged specAndrew Waterman68-419/+582
2015-02-08Use xlen, not xprlen, to refer to x-register widthAndrew Waterman19-35/+35
2015-01-27Fixed masking/casting logic in commit log printf.Christopher Celio1-5/+7
2015-01-26Fix commit logAndrew Waterman3-15/+15
2015-01-09Fix bug where C compiler used instead of C++ for autoconf testsStephen Twigg1-0/+2
2015-01-02Require 4-byte instruction alignment until RVC is reimplementedAndrew Waterman1-1/+2
2015-01-02On misaligned fetch, set EPC to target, not branch itselfAndrew Waterman4-10/+9
2015-01-02Reduce dependences on auto-generated codeAndrew Waterman5-14/+14
2014-12-04Support 2/4/6/8-byte instructionsAndrew Waterman3-41/+62
2014-12-04Set badvaddr on instruction page faultsAndrew Waterman3-5/+4
2014-12-03Update register names to match new ABIAndrew Waterman1-8/+8
2014-11-30Implement timer faithfullyAndrew Waterman9-56/+86
2014-11-25Factor out the dummy RoCC acceleratorAndrew Waterman5-137/+3
2014-11-22Revert "Enable support for the four custom instructions"Yunsup Lee25-72/+0
2014-11-19Add missing makefile dependenceAndrew Waterman1-1/+2
2014-10-30dummy-rocc-test build fixArun Thomas1-2/+2
2014-10-23Enable support for the four custom instructionsArun Thomas25-0/+72
2014-09-27Avoid some unused variable warningsAndrew Waterman3-15/+20
2014-09-27Avoid use of __int128_tAndrew Waterman10-22/+53
2014-09-20Update riscv.ac to set CPPFLAGS with fesvr include pathArun Thomas1-1/+1
2014-08-25clean up warnings from clangScott Beamer2-3/+1
2014-08-15Added PC histogram option.Christopher Celio5-1/+48
2014-08-07Support uarch counters (degenerately)Andrew Waterman1-0/+17
2014-07-24added support for register convention names in debug modeScott Beamer2-2/+23
2014-07-08Disallow access to FCSR when FP is disabledAndrew Waterman2-17/+24
2014-07-07Use precompiled headers to speed up compilationAndrew Waterman3-7/+10
2014-07-07Minor refactoringAndrew Waterman1-13/+13
2014-06-13Commit log now prints while interrupts are enabled.Christopher Celio2-14/+17
2014-06-13Only print commit log if instruction commitsAndrew Waterman3-5/+21
2014-06-12Set status.u64 to true on bootAndrew Waterman1-1/+1
2014-04-03Merge branch 'tm'Stephen Twigg1-3/+3
2014-04-03Sync encoding in opcodesStephen Twigg1-3/+15
2014-03-18Support RV32 RDTIMEH/RDCYCLEH/RDINSTRETHAndrew Waterman8-11/+29
2014-03-15speed up compilation a bitAndrew Waterman2-2/+2
2014-03-11New FP encodingAndrew Waterman1-42/+42
2014-03-06Add fclass.{s|d} instructionsAndrew Waterman3-0/+10
2014-02-25add extensions to riscv-dis for better disassemblyYunsup Lee1-1/+16
2014-02-14Renumber uarch CSRs into custom CSR spaceAndrew Waterman1-16/+16
2014-02-13Fix I$ simulator not making forward progressAndrew Waterman2-21/+17
generated by cgit v1.1 at 2024-07-11 10:33:33 +0000