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AgeCommit message (Expand)AuthorFilesLines
2022-04-12Move hartids into cfg_tRupert Swarbrick3-7/+11
2022-04-12Move the "default hartids" logic from sim.cc into spike.ccRupert Swarbrick1-10/+3
2022-04-12Move start_pc into cfg_tRupert Swarbrick3-5/+5
2022-04-12Fix debug messages about invalid pmpregions/mmu-typesRupert Swarbrick1-2/+2
2022-04-11Change processor_t to hold a pointer to an isa_parser_t (#973)Rupert Swarbrick3-17/+17
2022-04-11Split mem layout computation in spike.cc (#957)Rupert Swarbrick1-2/+29
2022-04-11Merge pull request #944 from riscv-software-src/triggersScott Johnson10-229/+389
2022-04-11Fix hgatp CSR writeAnup Patel1-1/+1
2022-04-11Merge pull request #968 from 4vtomat/masterAndrew Waterman1-84/+20
2022-04-10Adjust the access index of vs2 to zero in vmv_x_s.h (#969)Brandon Wu1-21/+17
2022-04-09Replaced vector loop compare body with newly defined macro4vtomat1-90/+11
2022-04-09Adding new macro to replace repetitive code4vtomat1-0/+15
2022-04-07Merge pull request #966 from riscv-software-src/fix-riscv-buildAndrew Waterman9-11/+11
2022-04-07Rename processor_t::set_csr to put_csr to fix build on RISC-VAndrew Waterman9-11/+11
2022-04-07Pass ref instead of pointer to trigger_updated()Tim Newsome3-5/+5
2022-04-07Add const to pointers where possible.Tim Newsome2-27/+27
2022-04-07Add module_t::~module_t()Tim Newsome2-0/+9
2022-04-06mmu: support asid/vmid (#928)Chih-Min Chao3-3/+13
2022-04-05Merge pull request #960 from marcfedorow/upstreamAndrew Waterman3-6/+15
2022-04-05Make triggers a vector of trigger_t.Tim Newsome3-3/+3
2022-04-05Abstract away access to load/store/execute bits.Tim Newsome3-18/+24
2022-04-05Make trigger_t::tdata{1,2}_{read,write} virtualsTim Newsome1-4/+9
2022-04-05Make chain into chain() for all triggers.Tim Newsome2-6/+10
2022-04-05Make triggers::module_t::triggers private.Tim Newsome4-6/+10
2022-04-05Move num_triggers knowledge into triggers.hTim Newsome4-10/+8
2022-04-05Don't access triggers vector directly from csrs.cc.Tim Newsome3-4/+29
2022-04-05Move trigger match logic into triggers.ccTim Newsome4-49/+71
2022-04-05module_t::trigger_match -> memory_access_matchTim Newsome3-4/+4
2022-04-05Move mcontrol match logic into mcontrol_t.Tim Newsome2-61/+62
2022-04-05trigger_matched_t -> triggers::matched_tTim Newsome3-19/+19
2022-04-05Give triggers::module_t its own processor_t*Tim Newsome4-4/+6
2022-04-05Move trigger_match() into triggers.Tim Newsome4-83/+89
2022-04-05Move tdata2 logic into trigger.Tim Newsome3-6/+16
2022-04-05Turn unsupported mcontrol.match into a supported one.Tim Newsome1-1/+14
2022-04-05V in misa implies FDMark Fedorov1-0/+1
2022-04-05Make misa.V writableMark Fedorov1-1/+3
2022-04-05Since ca08503 this code only runs at reset, so no longer depends on misa.V be...Mark Fedorov1-2/+2
2022-04-04Make misa.Q writableMark Fedorov1-1/+3
2022-04-04Refactor misa maskingMark Fedorov2-3/+7
2022-04-01update dts.cc to make sv57 default maximum paging mode (#962)Alenkruth Murali1-1/+1
2022-03-30Move tdata1 write logic into triggers.Tim Newsome3-23/+27
2022-03-30Move tdata1 read logic into triggers.cc.Tim Newsome3-19/+24
2022-03-30Make a few processor_t members const.Tim Newsome1-3/+3
2022-03-30Move tdata2 into mcontrol_tTim Newsome5-15/+8
2022-03-30Replace state.mcontrol with TM.triggers.Tim Newsome7-23/+45
2022-03-30Create trigger_t class.Tim Newsome1-3/+10
2022-03-30mcontrol_match_t -> mcontrol_t::match_tTim Newsome3-21/+21
2022-03-30Move mcontrol_t and mcontrol_match_t into triggersTim Newsome3-39/+39
2022-03-30mcontrol_action_t -> triggers::action_tTim Newsome4-13/+15
2022-03-30trigger_operation_t -> triggers::operation_tTim Newsome4-13/+22
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