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AgeCommit message (Expand)AuthorFilesLines
2020-10-06rvv: sstatus.SD needs to include vs dirty state (#563)Chih-Min Chao1-1/+2
2020-10-06Update SATP and HGATP mask usage to make it clearer (#564)Abhinay Kayastha1-3/+3
2020-10-04It should never be possible to select MPP=2Andrew Waterman1-1/+1
2020-10-01decode: only return meaningful bits for insn_t (#561)Chih-Min Chao1-1/+1
2020-09-29Adding symbol lookup when --enable-commitlog is enabled (#558)sthiruva6-0/+26
2020-09-28Add core id to lines generated by --log-commits (#556)sthiruva1-0/+4
2020-09-24pmp: fix local scope issue (#552)Chih-Min Chao1-3/+3
2020-09-24correctly respect mstatus.TW and hstatus.VTWAndrew Waterman1-2/+9
2020-09-24Correctly respect mstatus.TSRAndrew Waterman1-3/+6
2020-09-24Correctly respect mstatus.TVMAndrew Waterman3-7/+14
2020-09-24Fix priority of virtual vs. illegal instruction exceptions for HFENCEAndrew Waterman2-2/+2
2020-09-24Fix priority of virtual vs. illegal instruction exceptions for HLV/HSVAndrew Waterman13-13/+13
2020-09-23rvv: commitlog: add peek parameter to get_csrChih-Min Chao2-3/+7
2020-09-22rvv: fix vfncvt/vfwcvt type checkingChih-Min Chao16-16/+171
2020-09-22Separate build of spike and spike-dasmAndrew Waterman3-35/+4
2020-09-22Don't error out if dlopen isn't availableAndrew Waterman1-3/+1
2020-09-21Raise virtual-instruction traps correctly for WFI/SRET/SFENCEAndrew Waterman3-4/+6
2020-09-20Fix polarity of hstatus.HU fieldAndrew Waterman13-13/+13
2020-09-20Don't throw virtual instruction exceptions for unimplemented CSRsAndrew Waterman9-115/+133
2020-09-15rvv: fix int type is not enough to do shift (#544)Han-Kuan Chen2-2/+2
2020-09-15Populate tval registers on illegal-/virtual-instruction trapsAndrew Waterman9-20/+26
2020-09-15No need to catch illegal CSRs in set_csrAndrew Waterman1-16/+2
2020-09-11Add MIP_MEIP to all_ints (#543)Abhinay Kayastha1-1/+1
2020-09-01Fix MIDELEG and MEDELEG emulation when H-extension is available (#537)Anup Patel1-0/+7
2020-08-31rvv: reading vcsr needs to enable mstatus.vsChih-Min Chao1-0/+1
2020-08-31rvv: relax checking for vs1Chih-Min Chao3-2/+31
2020-08-31rvv: trigger exp for illegal ncvt/wcvt eewChih-Min Chao16-26/+26
2020-08-31rvv: check invalid frm for floating operationsChih-Min Chao3-0/+4
2020-08-31rvv: add reciprocal instructionsChih-Min Chao4-0/+30
2020-08-27rf: remove bit extraction from processor.hChih-Min Chao3-9/+18
2020-08-27rvv: remove quad instructionsChih-Min Chao11-60/+0
2020-08-20Fix debug tests failing with impebreak enabled. (#530)Tim Newsome1-1/+1
2020-08-20rvv: fix vrgatherei16 overlap ruleChih-Min Chao1-1/+2
2020-08-12mcounteren does not exist if U-mode is not implementedAndrew Waterman1-1/+4
2020-08-11Add option to dissable implicit ebreak in program bufferSamuel Obuch2-6/+10
2020-08-04Merge pull request #521 from chihminchao/op-hypvervisorAndrew Waterman3-51/+51
2020-08-03op: hyperviosr: fix exception code and nameChih-Min Chao3-6/+6
2020-08-03op: rearrange hypbervisor op/csr/causeChih-Min Chao1-46/+46
2020-08-03rvv: add 'vstartalu" option to --varch arugmentChih-Min Chao23-36/+45
2020-08-03op: rvv: fix pesudo code instructionsChih-Min Chao1-3/+3
2020-07-29f16: fix Nan-Box macroChih-Min Chao1-1/+1
2020-07-29rvv: fix frac_lmul get functionChih-Min Chao1-1/+1
2020-07-29rvv: remove isa string zvamoand zvlssegChih-Min Chao3-18/+0
2020-07-29rvv: remove veew/vemul stateChih-Min Chao3-32/+25
2020-07-29rvv: add vrgatherei16.vvChih-Min Chao3-0/+37
2020-07-29rvv: add new whole reg load/store instructionsChih-Min Chao24-21/+187
2020-07-29rvv: op: rearrange some instruction since generation order changeChih-Min Chao1-36/+36
2020-07-29rvv: op: fix amo namingChih-Min Chao38-144/+144
2020-07-29rvv: remove slenChih-Min Chao2-8/+5
2020-07-29rvv: initialize vector register as zeroChih-Min Chao1-1/+2
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