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2018-08-23Add dummy custom debug registers, to test OpenOCD. (#233)Tim Newsome2-0/+18
2018-08-23Fix several disassembler bugsAndrew Waterman1-0/+1
2018-08-23Add --disable-dtb option to suppress writing the DTB to memoryAndrew Waterman2-2/+7
2018-08-22Make IRQ_COP read-only/undelegable unless coprocessor is presentAndrew Waterman1-1/+2
2018-08-21Instantiate disassembler after max_xlen is knownAndrew Waterman1-1/+5
2018-08-17Don't increment instret immediately after it is written (#231)Andrew Waterman1-0/+6
2018-08-10Fix 2 trigger corner cases. (#229)Tim Newsome2-6/+14
2018-07-31Make sstatus.MXR readableAndrew Waterman1-1/+1
2018-07-23Fix using the uninitialized disassemble object. (#220)SeungRyeol Lee1-1/+1
2018-07-10Refactor and fix LR/SC implementation (#217)Andrew Waterman9-11/+34
2018-06-11Update debug_defines.hTim Newsome3-285/+303
2018-05-31Put simif_t declaration in its own file. (#209)Andy Wright7-16/+27
2018-05-18Fix install of missed header. (#207)Prashanth Mundkur1-0/+1
2018-05-18Extract out device-tree generation and compilation into an exported api. (#197)Prashanth Mundkur4-142/+175
2018-05-04Revert "C.LWSP and C.LDSP with rd=0 are legal instructions"Andrew Waterman2-0/+2
2018-05-03C.LWSP and C.LDSP with rd=0 are legal instructionsAndrew Waterman2-2/+0
2018-04-30Fix commit log for serializing instructionsAndrew Waterman1-1/+1
2018-04-30Only break out of the simulator loop on WFI, not on CSR writesAndrew Waterman3-2/+9
2018-04-04Allow querying the mmu configuration chosen during the build. (#191)Prashanth Mundkur1-0/+18
2018-04-04Revert "Fix for issue #183: No illegal instruction exception for c.sxxi instr...Andrew Waterman3-3/+3
2018-03-26Add an api to get the name for a CSR.Prashanth Mundkur2-0/+10
2018-03-21Implement Hauser misa.C misalignment proposal (#187)Andrew Waterman4-6/+12
2018-03-21Fix the access exception during page-table walks to match the original access...Prashanth Mundkur1-1/+9
2018-03-19Fix spike-dasm. (#184)Tim Newsome1-1/+2
2018-03-16Implement debug havereset bitsTim Newsome5-1/+33
2018-03-16Fix for issue #183: No illegal instruction exception for c.sxxi instructions ...Shubhodeep Roy Choudhury3-3/+3
2018-03-14Fix a bug caused by moving misa into state_t. (#180)Prashanth Mundkur2-3/+4
2018-03-13Move processor.isa to state.misa, since it really belongs there.Prashanth Mundkur2-10/+10
2018-03-09Fix single stepping csrrw instructions (#178)Tim Newsome1-8/+7
2018-03-07Merge pull request #177 from riscv/debug_authTim Newsome5-10/+52
2018-03-06Narrow the interface used by the processors and memory to the top-level simul...Prashanth Mundkur8-17/+28
2018-03-06Fix install of a missed header from debug_rom.Prashanth Mundkur2-2/+2
2018-03-06Fix a missed header file in the softfloat include install.Prashanth Mundkur1-0/+23
2018-03-03Implement clearing-misa.C-while-PC-is-misaligned proposalAndrew Waterman9-3/+15
2018-03-03Enforce 2-byte alignment of mepc/sepc/dpcAndrew Waterman1-3/+3
2018-03-01Merge pull request #173 from riscv/no_progbuf3Tim Newsome2-35/+98
2018-02-27Add debug module authentication.Tim Newsome5-10/+52
2018-02-21Don't allow 32-bit instructions to take up multiple slots in I$Andrew Waterman2-17/+4
2018-02-19Merge pull request #171 from riscv/sysbusbitsTim Newsome5-90/+293
2018-02-19Passes smoke tests with --progsize=0Tim Newsome1-15/+82
2018-02-19WIP. Doesn't work.Tim Newsome2-40/+36
2018-02-13Implement cycleh/instreth CSRs for RV32 (#172)Andrew Waterman1-0/+5
2018-02-01Add --debug-sba optionTim Newsome4-51/+44
2018-01-29Update debug_definesTim Newsome3-53/+53
2018-01-18Support debug system bus access.Tim Newsome5-20/+230
2018-01-09Use new debug_defines.h.Tim Newsome1-19/+19
2018-01-08mem_t: Throw an error if zero-sized memory is requested (#168)Jonathan Neuschäfer1-0/+2
2017-12-11Update debug_defines to latest version.Tim Newsome1-22/+48
2017-12-11Set impebreak.Tim Newsome2-1/+9
2017-12-11Update to latest debug_defines.h.Tim Newsome3-465/+411
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