| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2017-06-08 | Reset to "success" instead of "error."dtm_reset_error | Tim Newsome | 1 | -1/+1 | |
| OpenOCD actually checks this initial value now, and there's no reason for it to indicate error. | |||||
| 2017-06-07 | Forbid S-mode execution from user memory | Andrew Waterman | 1 | -2/+2 | |
| https://github.com/riscv/riscv-isa-manual/commit/285c81746fe664060b62ae0584865dbfa9f42e1a | |||||
| 2017-05-25 | minNum -> minimumNumber | Andrew Waterman | 4 | -8/+16 | |
| 2017-05-17 | Merge remote-tracking branch 'origin/priv-1.10' | Palmer Dabbelt | 91 | -2992/+3566 | |
| 2017-05-16 | Merge remote-tracking branch 'origin/debug-0.13' into priv-1.10 | Palmer Dabbelt | 17 | -2528/+2696 | |
| 2017-05-15 | Better error message when doing DMI operations and we're busy | Palmer Dabbelt | 1 | -2/+10 | |
| 2017-05-15 | debug: whitespace errors | Megan Wachs | 1 | -2/+2 | |
| 2017-05-15 | Merge branch 'debug-0.13' into HEAD | Megan Wachs | 1 | -0/+6 | |
| 2017-05-13 | Make C.LI/C.LUI trapping behavior match spec | Andrew Waterman | 2 | -2/+1 | |
| 2017-05-05 | UXL=SXL=MXL | Andrew Waterman | 2 | -4/+18 | |
| https://github.com/riscv/riscv-isa-manual/commit/326bec83de23f4d2daf24cfed6b5251748cad632 | |||||
| 2017-05-05 | Trap superpage PTEs when PPN LSBs are set | Andrew Waterman | 1 | -0/+2 | |
| 2017-05-03 | Add missing include for devices.h | Kito Cheng | 1 | -0/+2 | |
| - https://github.com/riscv/riscv-tools/issues/69 | |||||
| 2017-05-01 | Fix segfault when accessing bad memory addresses | Andrew Waterman | 3 | -11/+8 | |
| 2017-05-01 | Set default entry point from ELF | Andrew Waterman | 2 | -4/+8 | |
| 2017-04-30 | Add option to set start pc | Andrew Waterman | 2 | -9/+20 | |
| 2017-04-30 | Support more flexible main memory allocation | Andrew Waterman | 4 | -31/+59 | |
| 2017-04-30 | Store both host & target address in soft TLB | Andrew Waterman | 3 | -38/+47 | |
| 2017-04-26 | Remove a debugging printf | Palmer Dabbelt | 1 | -1/+0 | |
| 2017-04-26 | Don't spin on the remote bitbang reads | Palmer Dabbelt | 1 | -1/+1 | |
| 2017-04-26 | Handle abstractcs.busy | Palmer Dabbelt | 1 | -8/+10 | |
| 2017-04-26 | Have ndmreset reset the processor | Palmer Dabbelt | 1 | -0/+3 | |
| 2017-04-25 | FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.X | Andrew Waterman | 4 | -8/+8 | |
| 2017-04-25 | Remove hret instruction | Andrew Waterman | 1 | -3/+0 | |
| 2017-04-19 | Fix builds with "--enable-commitlog" | Palmer Dabbelt | 1 | -1/+1 | |
| 2017-04-18 | debug: move remote_bitbang into riscv | Megan Wachs | 2 | -0/+214 | |
| 2017-04-18 | debug: Remove duplicate remote_bitbang file | Megan Wachs | 2 | -208/+0 | |
| 2017-04-18 | debug: Able to successfully examine a single hart. | Megan Wachs | 1 | -1/+3 | |
| 2017-04-18 | debug: Use Debug-Module specific constants instead of global defines. | Megan Wachs | 3 | -45/+48 | |
| 2017-04-18 | debug: Checkpoint which somewhat works with OpenOCD v13, but still has some ↵ | Megan Wachs | 6 | -95/+107 | |
| bugs. | |||||
| 2017-04-17 | debug: Move things around, but addresses now conflict with ROM. | Megan Wachs | 5 | -119/+93 | |
| 2017-04-17 | debug: consider COMMAND.transfer bit, and implment HARTINFO | Megan Wachs | 1 | -9/+20 | |
| 2017-04-17 | debug: Compiles again with new debug_defines.h file, but not tested. | Megan Wachs | 2 | -12/+4 | |
| 2017-04-17 | debug: bump the debug_defines to match spec | Megan Wachs | 1 | -149/+61 | |
| 2017-04-17 | Merge remote-tracking branch 'origin/priv-1.10' into HEAD | Megan Wachs | 79 | -332/+747 | |
| 2017-04-10 | Implement new FP encoding | Andrew Waterman | 57 | -70/+93 | |
| https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/_r7hBlzsEd8/cWPyJKMzCQAJ | |||||
| 2017-04-07 | Implement vectored interrupt proposal | Andrew Waterman | 1 | -3/+5 | |
| https://github.com/riscv/riscv-isa-manual/commit/4dcaa944ba40e074d25516a157fc37f7491b71cc | |||||
| 2017-04-05 | Add --enable-misaligned option for misaligned ld/st support | Andrew Waterman | 2 | -4/+31 | |
| Resolves #93 | |||||
| 2017-03-31 | update encoding.h to get PMP updates | Yunsup Lee | 1 | -5/+6 | |
| 2017-03-30 | fdt: move interrupt controller into its own node | Wesley W. Terpstra | 1 | -4/+7 | |
| 2017-03-27 | Set badaddr=0 on illegal instruction traps | Andrew Waterman | 4 | -7/+7 | |
| 2017-03-27 | On EBREAK, set badaddr to pc | Andrew Waterman | 3 | -3/+3 | |
| 2017-03-27 | Separate page faults from physical memory access exceptions | Andrew Waterman | 4 | -13/+25 | |
| 2017-03-24 | Default to 2 GiB of memory | Andrew Waterman | 1 | -1/+1 | |
| 2017-03-23 | Require little-endian host | Andrew Waterman | 2 | -0/+14 | |
| 2017-03-22 | riscv: replace rtc device with a real clint implementation | Wesley W. Terpstra | 8 | -55/+96 | |
| 2017-03-21 | sim: declare cores as interrupt-controllers for clint | Wesley W. Terpstra | 1 | -0/+2 | |
| 2017-03-21 | bootrom: set a0 to hartid and a1 to dtb before boot | Wesley W. Terpstra | 1 | -7/+7 | |
| 2017-03-21 | configstring: rename variables to dts | Wesley W. Terpstra | 2 | -7/+7 | |
| 2017-03-21 | riscv: remove dependency on num_cores | Wesley W. Terpstra | 3 | -5/+1 | |
| 2017-03-21 | bootrom: include compiled dtb | Wesley W. Terpstra | 1 | -1/+87 | |
 |
index : rocket-tools/riscv-gnu-toolchain/spike.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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