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rocket-tools/riscv-gnu-toolchain/spike.git
confprec
cs250
cycleh
debug_rom
debug_rom_fence
device_flags
dtm_reset_error
dts_parsing
dynamic
eos18-bringup
factor-out-macros
fix-bf16
force-rtti
fp-encoding
heterogeneous_mc
hwachav4
increase-stack-size
itrigger-etrigger-cleanup
load_reservation_set_size
log-commits-faster
master
mmio-hack
mvp
no_progbuf
no_progbuf2
nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
plic-clint-endian
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pte-info-and-delegation
remove-tests
rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
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speed2
speedup-hacks
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test
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whole-archive
sifive/rvv0.9-phase2
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riscv
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sim.h
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Author
Files
Lines
2015-06-05
add an interactive "pc" command
Mike Frysinger
1
-0
/
+1
2015-06-05
unify interactive core processing
Mike Frysinger
1
-0
/
+1
2015-06-04
add a help screen to interactive mode
Mike Frysinger
1
-0
/
+1
2015-05-31
Use single, shared real-time counter
Andrew Waterman
1
-0
/
+2
2015-04-03
Support setting ISA/subsets with --isa flag
Andrew Waterman
1
-1
/
+3
2014-08-15
Added PC histogram option.
Christopher Celio
1
-0
/
+2
2014-01-13
Improve performance for branchy code
Andrew Waterman
1
-1
/
+2
2013-11-25
Update to new privileged ISA
Andrew Waterman
1
-1
/
+1
2013-10-28
Pass target machine's return code back to OS
Andrew Waterman
1
-1
/
+1
2013-10-18
refactor disassembler, and add hwacha disassembler
Yunsup Lee
1
-2
/
+3
2013-08-11
Instructions are no longer member functions
Andrew Waterman
1
-1
/
+1
2013-07-26
Generate instruction decoder dynamically
Andrew Waterman
1
-1
/
+1
2013-07-22
Add xspike program
Andrew Waterman
1
-0
/
+2
2013-07-12
Eliminate infinite loop in debug mode
Andrew Waterman
1
-0
/
+1
2013-07-12
Exit cleanly from debug console
Andrew Waterman
1
-6
/
+6
2013-04-23
destroy htif on simulator termination
Andrew Waterman
1
-1
/
+2
2013-03-29
add load-reserved/store-conditional instructions
Andrew Waterman
1
-10
/
+5
2013-03-25
add BSD license
Andrew Waterman
1
-0
/
+2
2013-02-13
add I$/D$/L2$ simulators
Andrew Waterman
1
-0
/
+1
2013-01-25
change htif to link against libfesvr
Andrew Waterman
1
-9
/
+7
2012-05-15
fix htif interaction with interactive mode
Andrew Waterman
1
-4
/
+1
2012-05-09
per-core tohost/fromhost registers
Andrew Waterman
1
-5
/
+0
2012-03-24
new supervisor mode
Andrew Waterman
1
-0
/
+1
2011-06-19
temporary undoing of renaming
Andrew Waterman
1
-0
/
+82
2011-06-12
[sim] renamed to riscv-isa-run
Andrew Waterman
1
-66
/
+0
2011-06-12
[xcc] minor performance tweaks
Andrew Waterman
1
-0
/
+1
2011-06-11
[xcc] cleaned up mmu code
Andrew Waterman
1
-4
/
+3
2011-05-28
[fesvr,xcc,sim] fixed multicore sim for akaros
Andrew Waterman
1
-0
/
+3
2011-04-30
[sim] hacked in a dcache simulator
Andrew Waterman
1
-1
/
+1
2011-04-16
[sim] added "str" debug command
Andrew Waterman
1
-0
/
+1
2011-04-15
[sim] added icache simulator (disabled by default)
Andrew Waterman
1
-0
/
+2
2010-09-08
[sim] add while to interactive_until
Yunsup Lee
1
-12
/
+13
2010-09-06
[sim] fixed bug in msub.d; added ability to print FPRs in debug mode
Andrew Waterman
1
-0
/
+3
2010-08-09
[sim] removed unused elf loader
Andrew Waterman
1
-1
/
+0
2010-07-21
[pk,sim] first cut of appserver communication link
Andrew Waterman
1
-5
/
+16
2010-07-18
Reorganized directory structure
Andrew Waterman
1
-0
/
+46
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