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path: root/riscv/sim.h
AgeCommit message (Expand)AuthorFilesLines
2020-05-20add configurable LR/SC reservation setDave.Wen1-0/+13
2020-05-19fdt: restructure dtb create and config flowChih-Min Chao1-9/+5
2020-05-19fdt: option: add --dtb option to specify dtb binary fileChih-Min Chao1-0/+5
2020-04-05Write execution logs to a named log file (#409)Rupert Swarbrick1-7/+16
2020-02-19Add optional support for real-time clintAnup Patel1-1/+2
2020-02-19Make spike capable of booting LinuxAnup Patel1-1/+3
2019-11-17Add --priv option to control which privilege modes are availableAndrew Waterman1-1/+2
2019-09-29Adds --log-commits commandline option. (#323)dave-estes-syzexion1-0/+2
2019-09-04Implement MMIO device plugins.Aaron Jones1-0/+2
2019-06-06rvv: refine trailing spaceChih-Min Chao1-1/+1
2019-05-29Clean up debug module options. (#299)Tim Newsome1-3/+1
2019-05-14Add --debug-no-abstract-csr (#267)Tim Newsome1-1/+1
2019-05-14Implement debug hasel support (#287)Tim Newsome1-1/+2
2019-05-14include sys/types.h for suseconds_t (#285)nmeum1-0/+1
2019-04-30rvv: configurable vector architecture during configuration andDave.Wen1-2/+2
2019-04-06Add --dmi-rti and --abstract-rti to test OpenOCD.Tim Newsome1-1/+2
2019-04-02rvv: support vector registers dumping under interactive modeDave.Wen1-0/+1
2018-10-18Provide a noisy until interactive commandHesham Almatary1-1/+3
2018-08-23Add --disable-dtb option to suppress writing the DTB to memoryAndrew Waterman1-0/+4
2018-05-31Put simif_t declaration in its own file. (#209)Andy Wright1-13/+1
2018-03-16Implement debug havereset bitsTim Newsome1-0/+5
2018-03-07Merge pull request #177 from riscv/debug_authTim Newsome1-1/+1
2018-03-06Narrow the interface used by the processors and memory to the top-level simul...Prashanth Mundkur1-1/+12
2018-02-27Add debug module authentication.Tim Newsome1-1/+1
2018-02-01Add --debug-sba optionTim Newsome1-1/+1
2018-01-18Support debug system bus access.Tim Newsome1-2/+7
2017-12-11Make progbuf a run-time option.Tim Newsome1-1/+2
2017-11-15Support for non-contiguous hartidsGleb Gagarin1-1/+1
2017-05-16Merge remote-tracking branch 'origin/debug-0.13' into priv-1.10Palmer Dabbelt1-5/+8
2017-05-01Set default entry point from ELFAndrew Waterman1-2/+2
2017-04-30Add option to set start pcAndrew Waterman1-1/+2
2017-04-30Support more flexible main memory allocationAndrew Waterman1-7/+4
2017-04-30Store both host & target address in soft TLBAndrew Waterman1-2/+1
2017-04-17Merge remote-tracking branch 'origin/priv-1.10' into HEADMegan Wachs1-5/+7
2017-04-10Implement new FP encodingAndrew Waterman1-1/+2
2017-03-22riscv: replace rtc device with a real clint implementationWesley W. Terpstra1-1/+1
2017-03-21configstring: rename variables to dtsWesley W. Terpstra1-3/+3
2017-03-21sim: define emulated CPU clock rate to be 1GHzWesley W. Terpstra1-0/+1
2017-02-10Entering debug mode now jumps to "dynamic rom"Tim Newsome1-0/+1
2017-02-07OpenOCD does a dmi read and gets dummy value back.Tim Newsome1-1/+2
2017-02-03OpenOCD connects, and sends some data that we receive.Tim Newsome1-4/+5
2016-06-22Remove legacy HTIF; implement HTIF directlyAndrew Waterman1-13/+20
2016-05-23Have Debug memory kind of working again.Tim Newsome1-3/+0
2016-05-23Add debug_module bus device.Tim Newsome1-6/+6
2016-05-23ROM -> RAM -> ROM, waiting for debug int.Tim Newsome1-0/+5
2016-05-23Add -H to start halted.Tim Newsome1-1/+1
2016-05-23gdb can now read spike memory.Tim Newsome1-0/+1
2016-05-23Listen on a socket for gdb to connect to.Tim Newsome1-0/+3
2016-05-02Remove tohost/fromhost registersAndrew Waterman1-2/+0
2016-04-30Remove SCRs; add padding after config stringAndrew Waterman1-7/+3