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path: root/riscv/sim.h
AgeCommit message (Expand)AuthorFilesLines
2016-06-22Remove legacy HTIF; implement HTIF directlyAndrew Waterman1-13/+20
2016-05-23Have Debug memory kind of working again.Tim Newsome1-3/+0
2016-05-23Add debug_module bus device.Tim Newsome1-6/+6
2016-05-23ROM -> RAM -> ROM, waiting for debug int.Tim Newsome1-0/+5
2016-05-23Add -H to start halted.Tim Newsome1-1/+1
2016-05-23gdb can now read spike memory.Tim Newsome1-0/+1
2016-05-23Listen on a socket for gdb to connect to.Tim Newsome1-0/+3
2016-05-02Remove tohost/fromhost registersAndrew Waterman1-2/+0
2016-04-30Remove SCRs; add padding after config stringAndrew Waterman1-7/+3
2016-04-29Move much closer to new platform-M memory mapAndrew Waterman1-3/+9
2016-04-28Add --dump-config-string flagAndrew Waterman1-0/+1
2016-04-28Remove MTIME[CMP]; add RTC deviceAndrew Waterman1-1/+2
2016-03-02Use RV config string rather than FDTAndrew Waterman1-2/+2
2015-11-12Generate device tree for target machineAndrew Waterman1-3/+4
2015-09-24Refactor memory access code; add MMIO supportAndrew Waterman1-0/+5
2015-08-06Add an option (-l) to display a log of execution in non-interactive mode.Prashanth Mundkur1-0/+2
2015-06-05add an interactive "pc" commandMike Frysinger1-0/+1
2015-06-05unify interactive core processingMike Frysinger1-0/+1
2015-06-04add a help screen to interactive modeMike Frysinger1-0/+1
2015-05-31Use single, shared real-time counterAndrew Waterman1-0/+2
2015-04-03Support setting ISA/subsets with --isa flagAndrew Waterman1-1/+3
2014-08-15Added PC histogram option.Christopher Celio1-0/+2
2014-01-13Improve performance for branchy codeAndrew Waterman1-1/+2
2013-11-25Update to new privileged ISAAndrew Waterman1-1/+1
2013-10-28Pass target machine's return code back to OSAndrew Waterman1-1/+1
2013-10-18refactor disassembler, and add hwacha disassemblerYunsup Lee1-2/+3
2013-08-11Instructions are no longer member functionsAndrew Waterman1-1/+1
2013-07-26Generate instruction decoder dynamicallyAndrew Waterman1-1/+1
2013-07-22Add xspike programAndrew Waterman1-0/+2
2013-07-12Eliminate infinite loop in debug modeAndrew Waterman1-0/+1
2013-07-12Exit cleanly from debug consoleAndrew Waterman1-6/+6
2013-04-23destroy htif on simulator terminationAndrew Waterman1-1/+2
2013-03-29add load-reserved/store-conditional instructionsAndrew Waterman1-10/+5
2013-03-25add BSD licenseAndrew Waterman1-0/+2
2013-02-13add I$/D$/L2$ simulatorsAndrew Waterman1-0/+1
2013-01-25change htif to link against libfesvrAndrew Waterman1-9/+7
2012-05-15fix htif interaction with interactive modeAndrew Waterman1-4/+1
2012-05-09per-core tohost/fromhost registersAndrew Waterman1-5/+0
2012-03-24new supervisor modeAndrew Waterman1-0/+1
2011-06-19temporary undoing of renamingAndrew Waterman1-0/+82
2011-06-12[sim] renamed to riscv-isa-runAndrew Waterman1-66/+0
2011-06-12[xcc] minor performance tweaksAndrew Waterman1-0/+1
2011-06-11[xcc] cleaned up mmu codeAndrew Waterman1-4/+3
2011-05-28[fesvr,xcc,sim] fixed multicore sim for akarosAndrew Waterman1-0/+3
2011-04-30[sim] hacked in a dcache simulatorAndrew Waterman1-1/+1
2011-04-16[sim] added "str" debug commandAndrew Waterman1-0/+1
2011-04-15[sim] added icache simulator (disabled by default)Andrew Waterman1-0/+2
2010-09-08[sim] add while to interactive_untilYunsup Lee1-12/+13
2010-09-06[sim] fixed bug in msub.d; added ability to print FPRs in debug modeAndrew Waterman1-0/+3
2010-08-09[sim] removed unused elf loaderAndrew Waterman1-1/+0
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