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2019-11-12Add --priv option to control which privilege modes are availableAndrew Waterman1-3/+4
2019-10-28Implement support for big-endian hostsMarcus Comstedt1-2/+5
2019-10-16Enforce 2^56-bit physical address limitAndrew Waterman1-2/+9
It's very difficult to encounter this (need to manually place a device or memory at very high addresses), but it is technically a Spike bug.
2019-09-18Adds --log-commits commandline option. (#323)dave-estes-syzexion1-1/+10
* Adds --log-commits commandline option. Similar to histogram support, the commit logging feature must be enabled with a configure option: --enable-commitlog. However, unlike that feature, there was no way to turn off the logging with a commandline option once the functionality was built in. This (git) commit provides that abilty. * Changes addressing review feedback.
2019-07-22Implement MMIO device plugins.Aaron Jones1-4/+8
2019-06-14rvv: add varch option parser and initialize vector unitChih-Min Chao1-4/+4
the default vector parameters are defined in configuration time but can be changed throught command-line option Signed-off-by: Dave Wen <dave.wen@sifive.com>
2019-05-14Clean up debug module options. (#299)Tim Newsome1-7/+3
* Clean up debug module options. 1. Instead of passing each one a few levels deep, create debug_module_config_t which contains them all. 2. Rename all those command line options so they start with --dm for debug module. 3. Add --dm-no-halt-groups to disable halt group support. * Update changelog.
2019-04-04Add --debug-no-abstract-csr (#267)Tim Newsome1-2/+4
This is used to make sure that OpenOCD can work on targets that don't support abstract access to CSR registers. It replaces a simpler hack, which caused #266.
2019-04-02Implement debug hasel support (#287)Tim Newsome1-2/+2
* Implement hasel/hawindow support. This should allow simultaneous resume and halt to work. * Fix anyrunning/anyhalted bits. * Add --without-hasel argument for testing. * Make halt/resume times more equal. Switching threads after every instruction executed in debug mode leads to a lot of extra instructions being executed on the "other" thread when both are really supposed to halt/resume near-simultaneously. Fixed that by adding wfi to debug_rom.S, and implementing it to switch to the other hart as well as check for JTAG input. When resuming, write the hart ID to the debug ROM so that the DM knows which hart actually resumed. (Before simultaneous resume it just assumed the current one.) Also got rid of resume symbol in debug_rom.S since it had no purpose. * Preserve Debug ROM entry points. * Make sure minstret is correct when wfi happens.
2018-12-13Add --dmi-rti and --abstract-rti to test OpenOCD.Tim Newsome1-2/+4
Optionally make spike behave more like real hardware, to automatically test OpenOCD's handling of such hardware.
2018-08-23Add --disable-dtb option to suppress writing the DTB to memoryAndrew Waterman1-2/+3
2018-07-10Refactor and fix LR/SC implementation (#217)Andrew Waterman1-1/+1
- Use physical addresses to avoid homonym ambiguity (closes #215) - Yield reservation on store-conditional (https://github.com/riscv/riscv-isa-manual/commit/03a5e722fc0fe7b94dd0a49f550ff7b41a63f612) - Don't yield reservation on exceptions (it's no longer required).
2018-05-18Extract out device-tree generation and compilation into an exported api. (#197)Prashanth Mundkur1-142/+2
2018-03-16Implement debug havereset bitsTim Newsome1-0/+5
2018-03-07Merge pull request #177 from riscv/debug_authTim Newsome1-2/+3
Add debug module authentication.
2018-03-06Narrow the interface used by the processors and memory to the top-level ↵Prashanth Mundkur1-3/+3
simulator/htif. This allows the implementation of an alternative top-level simulator class.
2018-02-27Add debug module authentication.Tim Newsome1-2/+3
Off by default, enabled with --debug-auth. The protocol is very simple (definitely not secure) to allow debuggers to test their authentication feature. To authenticate a debugger must: 1. Read authdata 2. Write to authdata the value that it just read, plus 1
2018-02-01Add --debug-sba optionTim Newsome1-2/+3
This lets the user control whether the system bus access implements bus mastering.
2018-01-18Support debug system bus access.Tim Newsome1-4/+3
2017-12-11Make progbuf a run-time option.Tim Newsome1-2/+4
Also add an implicit ebreak after the program buffer. This is not part of the spec, but hopefully it will be.
2017-11-15Merge pull request #156 from p12nGH/noncontiguous_hartsAndrew Waterman1-3/+14
Support for non-contiguous hartids
2017-11-15Support for non-contiguous hartidsGleb Gagarin1-3/+14
2017-11-03Put HTIF in the device treePalmer Dabbelt1-0/+3
I wanted to actually put the address of the HTIF into the DTS, but that seems to be a bit too much work: since the HTIF addresses are just defined in an ELF file it's a bit awkward to make that work. Instead, I'm just putting a dummy HTIF key in the DTS.
2017-06-14Support 64-bit start PCs in reset vector.Tim Newsome1-12/+10
2017-05-16Merge remote-tracking branch 'origin/debug-0.13' into priv-1.10Palmer Dabbelt1-6/+6
2017-05-01Fix segfault when accessing bad memory addressesAndrew Waterman1-2/+3
2017-05-01Set default entry point from ELFAndrew Waterman1-2/+6
2017-04-30Add option to set start pcAndrew Waterman1-8/+18
2017-04-30Support more flexible main memory allocationAndrew Waterman1-24/+21
2017-04-17Merge remote-tracking branch 'origin/priv-1.10' into HEADMegan Wachs1-48/+156
2017-03-30fdt: move interrupt controller into its own nodeWesley W. Terpstra1-4/+7
2017-03-24Default to 2 GiB of memoryAndrew Waterman1-1/+1
2017-03-22riscv: replace rtc device with a real clint implementationWesley W. Terpstra1-13/+11
2017-03-21sim: declare cores as interrupt-controllers for clintWesley W. Terpstra1-0/+2
2017-03-21bootrom: set a0 to hartid and a1 to dtb before bootWesley W. Terpstra1-7/+7
2017-03-21configstring: rename variables to dtsWesley W. Terpstra1-4/+4
2017-03-21bootrom: include compiled dtbWesley W. Terpstra1-1/+87
2017-03-21sim: create DTS instead of config stringWesley W. Terpstra1-26/+45
2017-02-13Abstract register read mostly working.Tim Newsome1-1/+1
Fails with not supported for 128-bit. Fails with exception (on rv32) with 64-bit. Succeeds (on rv32) with 32-bit.
2017-02-10Implement hartstatus field.Tim Newsome1-1/+1
2017-02-03OpenOCD connects, and sends some data that we receive.Tim Newsome1-4/+4
2016-12-16Use correct format codes for reg_t and size_tStefan O'Rear1-2/+2
Fixes 32-bit build.
2016-08-29Fix indent.Tim Newsome1-1/+1
2016-06-22Remove legacy HTIF; implement HTIF directlyAndrew Waterman1-14/+39
2016-05-23Make -H halt the core right out of reset.Tim Newsome1-3/+1
Added a test, too.
2016-05-23Have Debug memory kind of working again.Tim Newsome1-7/+2
Debug exception -> ROM -> RAM -> ROM, then something goes wrong.
2016-05-23Add debug_module bus device.Tim Newsome1-7/+8
This should replace the ROM hack I implemented earlier, but for now both exist together. Back to the point where gdb connects, core jumps to ROM->RAM->ROM.
2016-05-23Make sure to translate Debug RAM addresses also.Tim Newsome1-2/+3
2016-05-23Can jump to and execute Debug ROM.Tim Newsome1-1/+8
Connect with gdb, and the core will jump to Debug ROM and start executing it. Then it crashes when it jumps to 0x400 because Debug RAM isn't implemented (and doesn't live there anyway, for now).
2016-05-23Gutting direct-access gdb.Tim Newsome1-1/+1