aboutsummaryrefslogtreecommitdiff
path: root/riscv/sim.cc
AgeCommit message (Expand)AuthorFilesLines
2020-05-19Support consuming PMP number and granularity from DTBAndrew Waterman1-0/+9
2020-05-19fdt: restructure dtb create and config flowChih-Min Chao1-8/+45
2020-05-19fdt: option: add --dtb option to specify dtb binary fileChih-Min Chao1-2/+17
2020-04-05Fix debug segfault by partially reverting #409Andrew Waterman1-2/+3
2020-04-05Write execution logs to a named log file (#409)Rupert Swarbrick1-25/+33
2020-03-04rvv: remove the option of vector misaligned accessZhen Wei1-2/+0
2020-03-04rvv: remove the option of vector impl. checkZhen Wei1-4/+0
2020-02-19Make CLINT API use Hz instead of MHzAndrew Waterman1-1/+1
2020-02-19Add optional support for real-time clintAnup Patel1-2/+3
2020-02-19Make spike capable of booting LinuxAnup Patel1-3/+3
2019-11-17Add --priv option to control which privilege modes are availableAndrew Waterman1-3/+4
2019-10-29Implement support for big-endian hostsMarcus Comstedt1-2/+5
2019-10-22Enforce 2^56-bit physical address limitAndrew Waterman1-2/+9
2019-09-29Adds --log-commits commandline option. (#323)dave-estes-syzexion1-1/+10
2019-09-04rvv: exit when there is unsupported instructionsChih-Min Chao1-0/+1
2019-09-04rvv: reimplement check-1905 as check-implChih-Min Chao1-1/+3
2019-09-04Implement MMIO device plugins.Aaron Jones1-4/+8
2019-08-02rvv: add vector-mistrp optionChih-Min Chao1-2/+1
2019-06-06rvv: refine trailing spaceChih-Min Chao1-1/+1
2019-05-29Clean up debug module options. (#299)Tim Newsome1-7/+3
2019-05-20rvv: add --check-1905 option to turn on 1905 release checkChih-Min Chao1-0/+4
2019-05-14Add --debug-no-abstract-csr (#267)Tim Newsome1-2/+4
2019-05-14Implement debug hasel support (#287)Tim Newsome1-2/+2
2019-04-30rvv: configurable vector architecture during configuration andDave.Wen1-4/+4
2019-04-06Add --dmi-rti and --abstract-rti to test OpenOCD.Tim Newsome1-2/+4
2018-08-23Add --disable-dtb option to suppress writing the DTB to memoryAndrew Waterman1-2/+3
2018-07-10Refactor and fix LR/SC implementation (#217)Andrew Waterman1-1/+1
2018-05-18Extract out device-tree generation and compilation into an exported api. (#197)Prashanth Mundkur1-142/+2
2018-03-16Implement debug havereset bitsTim Newsome1-0/+5
2018-03-07Merge pull request #177 from riscv/debug_authTim Newsome1-2/+3
2018-03-06Narrow the interface used by the processors and memory to the top-level simul...Prashanth Mundkur1-3/+3
2018-02-27Add debug module authentication.Tim Newsome1-2/+3
2018-02-01Add --debug-sba optionTim Newsome1-2/+3
2018-01-18Support debug system bus access.Tim Newsome1-4/+3
2017-12-11Make progbuf a run-time option.Tim Newsome1-2/+4
2017-11-15Merge pull request #156 from p12nGH/noncontiguous_hartsAndrew Waterman1-3/+14
2017-11-15Support for non-contiguous hartidsGleb Gagarin1-3/+14
2017-11-03Put HTIF in the device treePalmer Dabbelt1-0/+3
2017-06-14Support 64-bit start PCs in reset vector.Tim Newsome1-12/+10
2017-05-16Merge remote-tracking branch 'origin/debug-0.13' into priv-1.10Palmer Dabbelt1-6/+6
2017-05-01Fix segfault when accessing bad memory addressesAndrew Waterman1-2/+3
2017-05-01Set default entry point from ELFAndrew Waterman1-2/+6
2017-04-30Add option to set start pcAndrew Waterman1-8/+18
2017-04-30Support more flexible main memory allocationAndrew Waterman1-24/+21
2017-04-17Merge remote-tracking branch 'origin/priv-1.10' into HEADMegan Wachs1-48/+156
2017-03-30fdt: move interrupt controller into its own nodeWesley W. Terpstra1-4/+7
2017-03-24Default to 2 GiB of memoryAndrew Waterman1-1/+1
2017-03-22riscv: replace rtc device with a real clint implementationWesley W. Terpstra1-13/+11
2017-03-21sim: declare cores as interrupt-controllers for clintWesley W. Terpstra1-0/+2
2017-03-21bootrom: set a0 to hartid and a1 to dtb before bootWesley W. Terpstra1-7/+7
generated by cgit v1.1 at 2024-07-11 10:32:28 +0000