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code and emits an error message to help avoid unintentionally loading wrong elf.
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the default target endian is always little endian:
- mmu::is_target_big_endian() return false
- sim_t::get_target_endianness() return memif_endianness_little
when RISCV_ENABLE_DUAL_ENDIAN macro is undefined
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The ns16550 is a widely use serial device so we add a simplified
ns16550 device emulation which is good enough for Linux, OpenSBI,
and hypervisors to use as console.
Signed-off-by: Anup Patel <anup@brainfault.org>
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We need an interrupt controller in Spike which will allow us to
emulate more real-world devices such as UART, VirtIO net, VirtIO
block, etc.
The RISC-V PLIC (or SiFive PLIC) is the commonly used interrupt
controller in existing RISC-V platforms so this patch adds PLIC
emulation for Spike.
Signed-off-by: Anup Patel <anup@brainfault.org>
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Now we have hartids, we can remove nprocs so that we have a single
source of truth.
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The only slightly difficult thing here is that hartids will always
be considered "overridden" by the time we get to sim_t::sim_t (either
overridden by a command line argument, or overridden when we set
default hartids just before the constructor). To allow downstream code
to distinguish between "I picked IDs 0, 1, 2, 3 because the user asked
for 4 processors" and "The user explicitly asked for IDs 0, 1, 2, 3",
we have an extra explicit_hartids field.
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This moves another part of the "configuration" out of the generic
sim.cc code.
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This was using the number of CPUs in total, rather than the CPU whose
PMP regions / MMU type it was actually parsing.
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Before, it had another copy, which is a little unnecessary.
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This commit defines a "cfg_t" structure, which currently just holds
the initrd address range. It will be augmented in future commits to
hold other configuration arguments as well.
To represent a configuration argument, we define an arg_t base class.
This holds a current value, together with a flag that tells us whether
the value has been updated from the default. The idea is that in
future we're going to use that flag when reading a DTB file: if an
argument has actually been specified on the command line, we need to
take it into account; if not, we can ignore the default and use the
DTB file's supplied value.
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This is a minor change, turning processor_t from a child class of
isa_parser_t into a class that contains an isa_parser_t as a field.
The point is that it is a step toward separating out
"configuration" (and ISA string parsing) from processor state. This
should be helpful for rejigging things so that we construct more from
a supplied device tree.
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If there is no 'mmu-type', we treat it as no mmu implementation
If there is no 'riscv,pmpregions', we treat it as no pmp implementation
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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We don't actually know that the field in the DTB points at a string
that's less than 256 bytes long, I don't think, so this could probably
cause a buffer overflow on the stack. Anyway, it turns out that
there's no need to copy anything anyway, so let's just update a char**
instead.
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This change makes it possible to faithfully simulate systems which
don't have a CLINT (without adding yet another command line argument
to pass through!).
Without a change like this, lowRISC has been using a local hack in its
Spike fork, where we've just commented out the internals of
clint_t::increment(). This approach is rather cleaner and is hopefully
general enough to use upstream.
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This catches silly mistakes like accidentally passing a DTS file when
it should have been a DTB.
Now, you get something like this:
$ /opt/spike/latest/bin/spike --dtb=bogus.dtb -l obj.o
Failed to read DTB from `bogus.dtb': FDT_ERR_BADMAGIC.
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This code is identical to make_dtb() which is called in the class
constructor, so I don't think we have to generate/load/parse things
again: we can just use the stuff we made earlier.
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sout is renamed to sout_ to reduce likelihood programmers accidentally use it.
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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For some reason, the old accessors for the non-sparse version were left
dangling. These methods are used by the --kernel and --initrd options,
and so those options were just broken.
This also fixes a memory leak and refactors the implementation a bit.
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This patch splites the target-requested memory regions into pages and only
allocates host memory when it is accessed to reduce larget memory sceniaro
in 64 bit target system
Co-authored-by: Dave.Wen <dave.wen@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Fix Issue #609 where extraneous debugging output was added when the user
invoked any simulation operation that involved addr_to_mem.
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Add a core parameter to the interactive str command. This makes it
possible for the spike user to specify the device whose memory contains
the NUL-terminated string to be printed.
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The original implementation only uses the value in first core and apply it
to other core. The patch makes the configuration hetergeneous for differenct
cores.
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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1. setup allowed mmu-type from dts
2. change default mmu-type in dts from sv39 to sv48
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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* Adding symbol lookup when --enable-commitlog is enabled
* Removed the #ifdef RISCV_ENABLE_COMMITLOG for all get_symbol related function
Only retained the in processor.cc where it is called.
Co-authored-by: Shajid Thiruvathodi <sthiruva@valtrix.in>
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We add bootargs command-line option to Spike which allows us to
provide custom kernel parameters to Linux and Xvisor.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
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The feature itself isn't implemented yet.
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1. pass dtb option from constructor
2. separate dtb generation from rom initialization
3. setup clint base from dtb
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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