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AgeCommit message (Expand)AuthorFilesLines
2020-05-19fdt: import fdt library from OpenSBIChih-Min Chao1-0/+1
2020-05-14rvv: add vzext/vsextChih-Min Chao1-0/+6
2020-05-13rvv: change to 0.9amoChih-Min Chao1-9/+36
2020-05-13rvv: amo pre-0.9Chih-Min Chao1-0/+12
2020-05-11rvv: change to 0.9 ldstChih-Min Chao1-44/+32
2020-05-04zfh: implementation all instructionsChih-Min Chao1-0/+39
2020-04-14rvv: add vfslide1[down|up].vf and refine checking ruleChih-Min Chao1-0/+2
2020-04-14rvv: add float conversion for rtz variantsChih-Min Chao1-0/+6
2020-01-06rvv : vmv[1248]r.vChih-Min Chao1-0/+4
2019-11-27rvv: add whole register load/store, vl1r.v/vs1r.vChih-Min Chao1-0/+2
2019-11-27rvv: add unsigned averageChih-Min Chao1-0/+4
2019-11-27rvv: replace vn suffic by 'w'Chih-Min Chao1-12/+12
2019-11-27rvv: rename vfncvt suffix and add rod rouding typeChih-Min Chao1-5/+6
2019-11-27rvv: add vqm* 'Quad-Widening Integer Multiply-Add'Chih-Min Chao1-0/+7
2019-11-27rvv: add quad insn and new vlenb csrChih-Min Chao1-7/+0
2019-11-17Re-encode vaadd/vasub; remove vaadd.vi; add vaaddu/vasubuAndrew Waterman1-1/+0
2019-10-22rvv: remove vmfordChih-Min Chao1-2/+0
2019-09-05rvv: change vext to vmvChih-Min Chao1-1/+1
2019-09-05Revert "vext.x.v -> vmv.x.s; unary operation encoding changes"Chih-Min Chao1-1/+1
2019-09-04Implement MMIO device plugins.Aaron Jones1-0/+3
2019-09-04vext.x.v -> vmv.x.s; unary operation encoding changesAndrew Waterman1-1/+1
2019-09-04vmfirst/vmpopc have been renamed to vfirst/vpopcAndrew Waterman1-2/+2
2019-07-22Remove old header from makefileAndrew Waterman1-1/+0
2019-07-22Fix support for 32-bit hosts (but no V extension in that case!)Andrew Waterman1-1/+1
2019-06-14rvv: sort instruction listChih-Min Chao1-16/+16
2019-06-13rvv: separte vfunary0 into independent instructionsChih-Min Chao1-1/+14
2019-06-13rvv: spearate vfunary1 into independent instructionsChih-Min Chao1-1/+2
2019-06-10rvv: fix vfw[add|sub].w[vf]Chih-Min Chao1-2/+3
2019-06-10rvv: fix widen fpu zero and functionChih-Min Chao1-0/+1
2019-06-09rvv: add missing targets vfwadd_vf and vfwadd_wfDave.Wen1-0/+2
2019-06-06rvv: follow new instruction name changeChih-Min Chao1-20/+18
2019-06-04rvv: sepapate vfmergeChih-Min Chao1-1/+2
2019-06-04rvv: add new adc/sbcChih-Min Chao1-0/+5
2019-06-04rvv: move vadc/vsbc.v[vxi] to vadc/vsbc.v[vxi]mChih-Min Chao1-5/+5
2019-06-04rvv: separate vmerge and vmvChih-Min Chao1-3/+6
2019-06-04rvv: vmiota_m -> viota_mChih-Min Chao1-1/+1
2019-06-04rvv: change vseq.?? to vmseq.?? and related insnsChih-Min Chao1-20/+20
2019-06-04rvv: add vfrsub.vfChih-Min Chao1-0/+1
2019-06-04rvv: change vfeq to vmfeq and related comparision instructionChih-Min Chao1-12/+12
2019-05-20rvv: change viota_m to vmiota_mChih-Min Chao1-1/+1
2019-05-19rvv: separate vmuary0 by new encoding changeChih-Min Chao1-1/+5
2019-05-16rvv: fix missng empty lineChih-Min Chao1-0/+1
2019-05-16rvv: fix integer reduction instruction suffixChih-Min Chao1-9/+8
2019-05-13Revert "Add FLH and FSH instructions expanding IEEE fp16 in memory to fp32 in...Chih-Min Chao1-2/+0
2019-05-13rvv: makefile spearate instruction for differenct extensionChih-Min Chao1-381/+422
2019-05-10rvv: add unordred indexed storeChih-Min Chao1-0/+4
2019-05-06rvv: add vwredsumChih-Min Chao1-0/+2
2019-05-02rvv: add vmunary0_vvChih-Min Chao1-0/+1
2019-05-01rvv: add fault-first only loadChih-Min Chao1-0/+7
2019-05-01rvv: add element load/storeChih-Min Chao1-0/+6
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