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path: root/riscv/riscv.mk.in
AgeCommit message (Expand)AuthorFilesLines
2017-02-15sfence.vm -> sfence.vmaAndrew Waterman1-1/+1
2016-06-22Remove legacy HTIF; implement HTIF directlyAndrew Waterman1-2/+0
2016-05-23Add dret.Tim Newsome1-0/+1
2016-05-23Add debug_module bus device.Tim Newsome1-0/+2
2016-05-23Listen on a socket for gdb to connect to.Tim Newsome1-0/+2
2016-05-19Removed devicetree.h from riscv.mk.in since it no longer existsacw12511-1/+0
2016-05-18Added missing header files to riscv.mk.inacw12511-0/+3
2016-04-28Remove MTIME[CMP]; add RTC deviceAndrew Waterman1-0/+2
2016-04-19Split ERET into URET, SRET, HRET, MRETAndrew Waterman1-2/+3
2016-03-02WIP on priv spec v1.9Andrew Waterman1-3/+0
2015-11-12Generate device tree for target machineAndrew Waterman1-0/+1
2015-10-20Update to hopefully final RVC 1.9 encodingAndrew Waterman1-2/+0
2015-10-05more work towards RVC 1.8Andrew Waterman1-2/+0
2015-10-02work towards rvc 1.8Andrew Waterman1-1/+11
2015-09-10Fix non-portable sed commands generating insn_list.hAlbert Ou1-1/+3
2015-09-08Improve instruction fetchAndrew Waterman1-1/+200
2015-05-13Install "disasm.h"Palmer Dabbelt1-0/+1
2015-04-03Support setting ISA/subsets with --isa flagAndrew Waterman1-1/+2
2015-01-02Reduce dependences on auto-generated codeAndrew Waterman1-2/+4
2014-11-25Factor out the dummy RoCC acceleratorAndrew Waterman1-1/+0
2014-11-19Add missing makefile dependenceAndrew Waterman1-1/+2
2014-09-27Avoid some unused variable warningsAndrew Waterman1-2/+3
2014-09-27Avoid use of __int128_tAndrew Waterman1-0/+1
2014-07-07Use precompiled headers to speed up compilationAndrew Waterman1-0/+4
2014-01-26Eliminate hwacha <-> riscv circular dependenceAndrew Waterman1-5/+0
2014-01-25Merge softfloat_riscv into softfloatAndrew Waterman1-1/+0
2014-01-13Improve performance for branchy codeAndrew Waterman1-0/+4
2013-11-25Update to new privileged ISAAndrew Waterman1-5/+5
2013-10-16revamp hwacha; now runs in physical modeYunsup Lee1-0/+1
2013-09-15Add helper disassembly programAndrew Waterman1-0/+1
2013-08-13Implement RoCC and add a dummy RoCCAndrew Waterman1-0/+5
2013-07-26Generate instruction decoder dynamicallyAndrew Waterman1-13/+9
2013-07-22Add xspike programAndrew Waterman1-0/+2
2013-06-02use coreutils `seq' instead of hacky `range'Andrew Waterman1-1/+1
2013-05-15fix make issueYunsup Lee1-3/+3
2013-05-13change riscv-isa-run to spikeYunsup Lee1-1/+1
2013-05-06make Makefile sh-friendlyAndrew Waterman1-1/+1
2013-04-24fix(?) circular dependence on generated headersAndrew Waterman1-22/+19
2013-04-22correctly depend on dispatch.hAndrew Waterman1-10/+5
2013-04-19remove circular dependence in MakefileAndrew Waterman1-4/+8
2013-04-17add AUIPC insn; remove RDNPC insnAndrew Waterman1-1/+1
2013-02-13add I$/D$/L2$ simulatorsAndrew Waterman1-1/+3
2011-11-11Remove dependence on binutilsYour Name1-0/+1
2011-06-19temporary undoing of renamingAndrew Waterman1-0/+50
2011-06-12[sim] renamed to riscv-isa-runAndrew Waterman1-60/+0
2011-06-11[xcc] fixed simulator build timeAndrew Waterman1-1/+22
2011-06-10[sim, opcodes] made sim more decoupled from opcodesAndrew Waterman1-12/+14
2011-05-29[sim,opcodes] improved sim build and run performanceAndrew Waterman1-3/+13
2011-05-16[sim,pk] cleanups & initial virtual memory supportAndrew Waterman1-0/+1
2011-04-15[sim] added icache simulator (disabled by default)Andrew Waterman1-0/+1
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