aboutsummaryrefslogtreecommitdiff
path: root/riscv/riscv.mk.in
AgeCommit message (Expand)AuthorFilesLines
2020-07-29rvv: add vrgatherei16.vvChih-Min Chao1-0/+1
2020-07-29rvv: add new whole reg load/store instructionsChih-Min Chao1-1/+19
2020-07-29rvv: op: fix amo namingChih-Min Chao1-36/+36
2020-07-09Implement new instructions of hypervisor extensionAnup Patel1-0/+18
2020-06-16zfh: implement all instructionsChih-Min Chao1-1/+40
2020-06-10ext: build libriscv PIC to make it linkable to ext libraryChih-Min Chao1-0/+2
2020-05-28rvv: add new explicit eew load/store instructionsChih-Min Chao1-44/+32
2020-05-28rvv: add amo instructionsChih-Min Chao1-0/+39
2020-05-28rvv: add new singed/unsiged extension instructionsChih-Min Chao1-0/+6
2020-04-26fdt: import fdt library from OpenSBIChih-Min Chao1-0/+1
2020-04-24rvv: add vfslide1[down|up].vf and refine checking ruleChih-Min Chao1-0/+2
2020-04-20rvv: add float conversion for rtz variantsChih-Min Chao1-0/+6
2020-01-13rvv: add vmv[1248]r.vChih-Min Chao1-0/+4
2019-12-20rvv: add unsigned averageChih-Min Chao1-0/+4
2019-12-20rvv: replace vn suffic by 'w'Chih-Min Chao1-12/+12
2019-12-20rvv: add load/store whole register instructionsChih-Min Chao1-0/+2
2019-12-20rvv: rename vfncvt suffix and add rod rouding typeChih-Min Chao1-5/+6
2019-12-20rvv: add vqm* 'Quad-Widening Integer Multiply-Add'Chih-Min Chao1-0/+7
2019-12-20rvv: add quad insn and new vlenb csrChih-Min Chao1-7/+0
2019-11-15Re-encode vaadd/vasub; remove vaadd.vi; add vaaddu/vasubuAndrew Waterman1-1/+0
2019-11-11rvv: fix vmv.x.s signed-ext issueChih-Min Chao1-1/+1
2019-10-29rvv: remove vmfordChih-Min Chao1-2/+0
2019-07-22Implement MMIO device plugins.Aaron Jones1-0/+3
2019-07-19vext.x.v -> vmv.x.s; unary operation encoding changesAndrew Waterman1-1/+1
2019-07-12Remove old header from makefileAndrew Waterman1-1/+0
2019-07-11Fix support for 32-bit hosts (but no V extension in that case!)Andrew Waterman1-1/+1
2019-07-05vmfirst/vmpopc have been renamed to vfirst/vpopcAndrew Waterman1-2/+2
2019-06-18rvv: add floating-point instructionsChih-Min Chao1-0/+96
2019-06-18rvv: add load/store instructionsChih-Min Chao1-0/+47
2019-06-18rvv: add integer/fixed-point/mask/reduction/permutation instructionsChih-Min Chao1-0/+206
2019-06-18rvv: add control instructions and system register accessChih-Min Chao1-0/+8
2019-06-09rvv: re-arrange instruction list by different extensionChih-Min Chao1-129/+155
2018-05-31Put simif_t declaration in its own file. (#209)Andy Wright1-0/+1
2018-05-18Fix install of missed header. (#207)Prashanth Mundkur1-0/+1
2018-05-18Extract out device-tree generation and compilation into an exported api. (#197)Prashanth Mundkur1-0/+2
2017-09-28Implement Q extensionAndrew Waterman1-0/+32
2017-05-16Merge remote-tracking branch 'origin/debug-0.13' into priv-1.10Palmer Dabbelt1-2/+4
2017-04-25FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.XAndrew Waterman1-2/+2
2017-04-17debug: Compiles again with new debug_defines.h file, but not tested.Megan Wachs1-2/+0
2017-04-17Merge remote-tracking branch 'origin/priv-1.10' into HEADMegan Wachs1-1/+3
2017-03-22riscv: replace rtc device with a real clint implementationWesley W. Terpstra1-1/+1
2017-02-15sfence.vm -> sfence.vmaAndrew Waterman1-1/+1
2017-02-06Refactor remote bitbang code.Tim Newsome1-0/+2
2017-02-03OpenOCD connects, and sends some data that we receive.Tim Newsome1-2/+2
2016-06-22Remove legacy HTIF; implement HTIF directlyAndrew Waterman1-2/+0
2016-05-23Add dret.Tim Newsome1-0/+1
2016-05-23Add debug_module bus device.Tim Newsome1-0/+2
2016-05-23Listen on a socket for gdb to connect to.Tim Newsome1-0/+2
2016-05-19Removed devicetree.h from riscv.mk.in since it no longer existsacw12511-1/+0
2016-05-18Added missing header files to riscv.mk.inacw12511-0/+3