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rocket-tools/riscv-gnu-toolchain/spike.git
confprec
cs250
cycleh
debug_rom
debug_rom_fence
device_flags
dtm_reset_error
dts_parsing
dynamic
eos18-bringup
factor-out-macros
fix-bf16
force-rtti
fp-encoding
heterogeneous_mc
hwachav4
increase-stack-size
itrigger-etrigger-cleanup
load_reservation_set_size
log-commits-faster
master
mmio-hack
mvp
no_progbuf
no_progbuf2
nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
plic-clint-endian
plic_uart_v1
priv-1.10
private-l1-caches
pte-info-and-delegation
remove-tests
rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
sparse-mem
speedup-hacks
static-link
test
tmp
trigger_priority
tweak_debug_rom
whole-archive
sifive/rvv0.9-phase2
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riscv-isa-run.cc
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Author
Files
Lines
2013-05-13
change riscv-isa-run to spike
Yunsup Lee
1
-62
/
+0
2013-03-25
add BSD license
Andrew Waterman
1
-0
/
+2
2013-02-15
specialize fully-associative caches
Andrew Waterman
1
-1
/
+1
2013-02-13
add I$/D$/L2$ simulators
Andrew Waterman
1
-29
/
+37
2013-01-25
change htif to link against libfesvr
Andrew Waterman
1
-20
/
+15
2012-01-31
remove debug printf
Andrew Waterman
1
-1
/
+0
2012-01-31
poll HTIF occasionally
Andrew Waterman
1
-0
/
+1
2011-07-13
added #include <stdlib.h> to get rid of errors building with gcc-4.4 on ubuntu
Rimas Avizienis
1
-0
/
+1
2011-06-19
temporary undoing of renaming
Andrew Waterman
1
-0
/
+56
2011-06-12
[sim] renamed to riscv-isa-run
Andrew Waterman
1
-63
/
+0
2011-06-11
[xcc] cleaned up mmu code
Andrew Waterman
1
-1
/
+1
2011-04-30
[sim] hacked in a dcache simulator
Andrew Waterman
1
-3
/
+21
2011-04-15
[sim] added icache simulator (disabled by default)
Andrew Waterman
1
-1
/
+7
2010-07-22
[sim] various fixes to get the sim work with the fesvr
Yunsup Lee
1
-1
/
+1
2010-07-21
[pk,sim] first cut of appserver communication link
Andrew Waterman
1
-8
/
+20
2010-07-18
Reorganized directory structure
Andrew Waterman
1
-0
/
+27