aboutsummaryrefslogtreecommitdiff
path: root/riscv/processor.h
AgeCommit message (Collapse)AuthorFilesLines
2016-05-23Gutting direct-access gdb.Tim Newsome1-8/+2
2016-05-23Add writing to DCSR, DPC, DSCRATCH.Tim Newsome1-0/+17
Make those 3 CSRs writable.
2016-05-23Flush icache when using swbps and report to gdb.Tim Newsome1-1/+11
2016-05-23Looks like single step works.Tim Newsome1-0/+4
2016-05-23Now you can halt/continue from gdb.Tim Newsome1-0/+4
2016-05-23gdb can now read spike memory.Tim Newsome1-0/+1
The endianness is wrong, but I think it might be that gdb doesn't have it right. Need to investigate what architecture gdb thinks it's debugging.
2016-05-02Remove tohost/fromhost registersAndrew Waterman1-2/+0
2016-04-29Move much closer to new platform-M memory mapAndrew Waterman1-0/+1
Reset vector is at 0x1000; below that is reserved for debug Memory is at 0x80000000
2016-04-28Remove MTIME[CMP]; add RTC deviceAndrew Waterman1-1/+1
2016-03-02Add counter-enable registersAndrew Waterman1-0/+2
2016-03-02WIP on priv spec v1.9Andrew Waterman1-2/+0
2016-03-02New definitions of misa/marchid/mvendoridAndrew Waterman1-3/+3
2016-03-02WIP on priv spec v1.9Andrew Waterman1-4/+6
2015-12-17another osx clang compatability fixScott Beamer1-1/+1
2015-11-12Generate device tree for target machineAndrew Waterman1-2/+8
2015-10-26Fix histogram for RVCAndrew Waterman1-2/+2
No need to right-shift PC by 2. It's a map, so this is a false economy.
2015-09-15commit log now correctly prints privilegeScott Beamer1-0/+1
adopting convention of privilege at time of commit, not after commit
2015-09-08Improve instruction fetchAndrew Waterman1-4/+6
- Performance for variable-length instructions is much better - Refill is simpler and faster - Support for instructions with overlapping opcodes (e.g. C.ADD + C.JALR)
2015-07-05New machine-mode timer facilityAndrew Waterman1-2/+1
2015-05-31Use single, shared real-time counterAndrew Waterman1-2/+5
This required disentangling INSTRET/CYCLE from TIME.
2015-05-31Take interrupts as soon as interrupts are enabledAndrew Waterman1-1/+1
Previously, if interrupts were enabled then disabled quickly enough, no interrupt would ever be taken, resulting in deadlock.
2015-05-09Upgrade to privileged architecture 1.7Andrew Waterman1-4/+8
2015-04-03Support setting ISA/subsets with --isa flagAndrew Waterman1-1/+5
Default is RV64IMAFDC. Can do things like --isa=RV32 (which implies IMAFDC) --isa=IM (which implies RV64) --isa=RV64IMAFDXhwacha
2015-03-26Serialize counters without throwing C++ exceptionsAndrew Waterman1-2/+1
Ideally, a similar mechanism will apply to target machine exceptions.
2015-03-12Update to new privileged specAndrew Waterman1-15/+20
Sorry, everyone.
2015-01-26Fix commit logAndrew Waterman1-1/+1
I screwed up some stuff in a recent refactoring.
2014-11-30Implement timer faithfullyAndrew Waterman1-2/+4
rdcycle/rdinstret now have single-instruction granularity. Questionable behavior when timer interrupts occurred around the same time as the compare register is written should be fixed.
2014-08-15Added PC histogram option.Christopher Celio1-0/+5
- Spits out all PCs (on 4B granularity) executed with count. - Requires a compile time configuration option. - Also requires a run-time flag.
2014-06-13Only print commit log if instruction commitsAndrew Waterman1-0/+10
2014-03-15speed up compilation a bitAndrew Waterman1-2/+1
2014-01-13Improve performance for branchy codeAndrew Waterman1-2/+2
We now use a heavily unrolled loop as the software I$, which allows the host machine's branch target prediction to associate target PCs with unique-ish host PCs.
2013-12-17Speed things up quite a bitAndrew Waterman1-6/+10
2013-11-25Update to new privileged ISAAndrew Waterman1-8/+5
2013-10-18refactor disassembler, and add hwacha disassemblerYunsup Lee1-4/+7
2013-08-13Implement RoCC and add a dummy RoCCAndrew Waterman1-12/+25
Enable it with --extension=dummy
2013-08-11Instructions are no longer member functionsAndrew Waterman1-32/+37
2013-07-26Remove more vector stuffAndrew Waterman1-21/+0
2013-07-26Rip out RVC for nowAndrew Waterman1-14/+0
2013-07-26Generate instruction decoder dynamicallyAndrew Waterman1-7/+26
This will make it easier for accelerators to add instructions.
2013-03-29add load-reserved/store-conditional instructionsAndrew Waterman1-5/+0
2013-03-25add BSD licenseAndrew Waterman1-0/+2
2013-03-25expose pending interrupts in status registerAndrew Waterman1-1/+1
2013-02-13add I$/D$/L2$ simulatorsAndrew Waterman1-0/+1
2013-01-25change htif to link against libfesvrAndrew Waterman1-1/+1
2012-08-30new tohost/fromhost semanticsAndrew Waterman1-0/+1
2012-07-22correct HTIF reset behaviorAndrew Waterman1-3/+2
cores' reset signals can be independently toggled
2012-05-09per-core tohost/fromhost registersAndrew Waterman1-3/+6
update your fesvr
2012-03-24new supervisor modeAndrew Waterman1-4/+5
2012-03-19abstract regfile behind objectAndrew Waterman1-2/+2
2012-01-22disentangle decode.h from other headersAndrew Waterman1-0/+15
generated by cgit v1.1 at 2024-07-11 12:16:35 +0000