rocket-tools/riscv-gnu-toolchain/spike.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-05-22	rvv: totally remove vlmul field	Chih-Min Chao	1	-1/+0
2020-05-22	rvv: remove remove vlmul	Chih-Min Chao	1	-1/+1
2020-05-21	rvv: remove vmlen	Chih-Min Chao	1	-1/+1
2020-05-20	add configurable LR/SC reservation set	Dave.Wen	1	-1/+1
2020-05-19	Implement CSR read/write behavior for coarse-grain PMP	Andrew Waterman	1	-0/+2
2020-05-19	Support consuming PMP number and granularity from DTB	Andrew Waterman	1	-0/+6
2020-05-19	Rename n_pmp constant to max_pmp	Andrew Waterman	1	-3/+3
2020-05-13	rvv: fractional_lmul when lmul < 1	Dave.Wen	1	-0/+1
2020-05-07	rvv: add eew and lmul for vle/vse/vleff	Dave.Wen	1	-0/+3
2020-05-06	fractional_lmul: update the vtype register and alos remove the useless reg_mask	Dave.Wen	1	-1/+3
2020-04-14	parser: extend --isa to support extended extension	Chih-Min Chao	1	-2/+15
2020-04-05	Write execution logs to a named log file (#409)	Rupert Swarbrick	1	-3/+9
2020-03-05	rvv: avoid redundant std::string comparison	Zhen Wei	1	-1/+8
2020-03-05	rvv: import parallel vf(w)redsum hardware impl.	Zhen Wei	1	-0/+3
2020-03-04	rvv: remove the option of vector impl. check	Zhen Wei	1	-4/+3
2020-02-12	rvv: remove duplicate vectorUnit declaration	Chih-Min Chao	1	-58/+3
2020-02-12	debug: refine per-inst difference record	Chih-Min Chao	1	-8/+10
2020-02-12	commitlog: rvv: change vector register read/write interface	Chih-Min Chao	1	-0/+59
2020-02-12	commitlog: extend reg record to keep multiple accesss	Chih-Min Chao	1	-5/+3
2020-02-12	commitlog: extend load/store record to keep multiple access	Chih-Min Chao	1	-6/+2
2019-12-19	extend the commit and memory writes log feature with memory reads (#370)	John Ingalls	1	-0/+1
2019-11-27	rvv: change vsetvl[i] to match 0.8 spec	Chih-Min Chao	1	-1/+1
2019-11-27	rvv: add read-only vleb csr	Chih-Min Chao	1	-1/+1
2019-11-17	Add --priv option to control which privilege modes are available	Andrew Waterman	1	-4/+5
2019-11-11	rvv: remove tail-zero	Chih-Min Chao	1	-1/+1
2019-10-29	Implement support for big-endian hosts	Marcus Comstedt	1	-0/+5
2019-10-15	rvv: add new rs1 = zero feature to vsetvl	Chih-Min Chao	1	-1/+1
2019-10-08	Fixed match trigger MATCH_NAPOT case. (#335)	fborisovskii	1	-1/+1
2019-09-29	Extends the commit log feature with memory writes. (#324)	dave-estes-syzexion	1	-0/+8
2019-09-29	Adds --log-commits commandline option. (#323)	dave-estes-syzexion	1	-0/+3
2019-09-25	rvv:add t0/t1 to configure to setup default tailzero mode	Chih-Min Chao	1	-1/+1
2019-09-04	rvv: add impl_table for instruction release check	Chih-Min Chao	1	-3/+4
2019-07-22	Writing non-existent CSRs, access FPRs with mstatus.FS=0 (#311)	Tim Newsome	1	-1/+1
2019-07-22	Add debug_mode state bit, rather than overloading dcsr.cause	Andrew Waterman	1	-2/+4
2019-06-12	rvv: merge the vcsr to ordinary csr and remove the redundant functions	Dave.Wen	1	-2/+0
2019-06-12	WIP: move from gamma07 to gamma03	Dave.Wen	1	-1/+2
2019-06-06	rvv: remove old register boundary checking	Chih-Min Chao	1	-5/+1
2019-06-06	rvv: remove trailing space	Chih-Min Chao	1	-1/+1
2019-06-04	rvv: refine the code for checking the varch option set	Dave.Wen	1	-3/+0
2019-04-30	rvv: fixed type and removed redundant variable	Dave.Wen	1	-2/+2
2019-04-30	rvv: decouple the vectorUnit to the processor's state.	Dave.Wen	1	-61/+67
2019-04-25	rvv: fix vsmulv[vx]	Dave.Wen	1	-3/+1
2019-04-22	fixed type RUN to RNU	Dave.Wen	1	-1/+1
2019-04-20	improve the vectorUint_t	Dave	1	-5/+8
2019-04-15	Revert "Revert "rvv: restore reg_reference keeping""	Chih-Min Chao	1	-0/+3
2019-04-15	Revert "rvv: restore reg_reference keeping"	Chih-Min Chao	1	-3/+0
2019-04-15	rvv: restore reg_reference keeping	Chih-Min Chao	1	-0/+3
2019-04-10	rvv: simplify register offset calculation	Chih-Min Chao	1	-3/+0
2019-04-07	rvv: add unsigned sew type	Dave.Wen	1	-0/+28
2019-03-31	rvv: rewrite the vector destination for varies sew	Dave.Wen	1	-0/+27