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2022-10-17Merge branch 'master' into plic_uart_v1plic_uart_v1Andrew Waterman1-15/+19
2022-10-04Suppress most unused variable warningsAndrew Waterman1-1/+1
2022-10-04Fix unused-function warning on sometimes-used function ctoAndrew Waterman1-1/+1
2022-09-20Merge pull request #1036 from plctlab/plct-sscofpmf-devAndrew Waterman1-0/+1
add support for sscofpmf extension v0.5.2
2022-09-08Remove obsolete enum trigger_operation_tScott Johnson1-6/+0
Moved to triggers.h and renamed in a2a2587426e57f6207d5389620e9109bc0f82e6b, but the old enum was mistakenly left behind.
2022-08-10Add space between if/while/switch and '('Weiwei Li1-2/+2
Add space between ')' and '{'
2022-08-09add support for sscofpmf extension v0.5.2Weiwei Li1-0/+1
since spike doesn't truly support counting of hardware performance events, only csr related read/write functions is supported currently
2022-08-03Add Sstc support. (#1057)i2h21-0/+4
2022-07-21add support for time/timeh/htimedelta/htimedeltah csrsWeiwei Li1-0/+3
2022-07-13Properly log mstatush side effect updatesScott Johnson1-0/+1
These have never been logged properly.
2022-07-09add support for csrs of smstateen extensionsWeiwei Li1-0/+4
2022-07-07remove multi blank linesWeiwei Li1-1/+0
2022-05-12Remove insn_func_t::supported fieldAndrew Waterman1-5/+1
The field is rendered unnecessary by 11f5942b7d8211e61b5ad9259d118033692c0759. Undoes some changes from 750f008e723bb3b20cec41a47ed5cec549447665.
2022-05-04Implement the new csr mseccfg for ePMP as dummysoberl@nvidia.com1-0/+2
2022-04-20Add PLIC emulationAnup Patel1-0/+1
We need an interrupt controller in Spike which will allow us to emulate more real-world devices such as UART, VirtIO net, VirtIO block, etc. The RISC-V PLIC (or SiFive PLIC) is the commonly used interrupt controller in existing RISC-V platforms so this patch adds PLIC emulation for Spike. Signed-off-by: Anup Patel <anup@brainfault.org>
2022-04-14add support for overlap instructionsWeiwei Li1-1/+5
* add DECLARE_OVERLAP_INSN to bind instructions with extension * add overlap_list.h to contain the declare of all overlapping instructions * make func function for overlapping instruction return NULL when the coresponding extension(s) is not supported.
2022-04-11Change processor_t to hold a pointer to an isa_parser_t (#973)Rupert Swarbrick1-5/+5
Before, it had another copy, which is a little unnecessary.
2022-04-11Merge pull request #944 from riscv-software-src/triggersScott Johnson1-126/+6
Refactor trigger code
2022-04-07Rename processor_t::set_csr to put_csr to fix build on RISC-VAndrew Waterman1-1/+1
The alternative would be to #undef set_csr after including encoding.h, but this solution strikes me as cleaner. Part of the reason is that set_csr was not a great name: it sounds like it implements the CSRRS (read & set) instruction, rather than impelementing a simple write.
2022-04-07Pass ref instead of pointer to trigger_updated()Tim Newsome1-1/+1
2022-04-05Make triggers a vector of trigger_t.Tim Newsome1-1/+1
Not just mcontrol_t.
2022-04-05Make triggers::module_t::triggers private.Tim Newsome1-1/+1
2022-04-05Move num_triggers knowledge into triggers.hTim Newsome1-2/+0
2022-04-05Move trigger_match() into triggers.Tim Newsome1-81/+0
2022-03-30Make a few processor_t members const.Tim Newsome1-3/+3
Members: get_xlen(), get_const_xlen(), get_flen() That doesn't mean the value they return will never be changed, but merely that those functions don't modify the processor_t object when called.
2022-03-30Move tdata2 into mcontrol_tTim Newsome1-1/+1
2022-03-30Replace state.mcontrol with TM.triggers.Tim Newsome1-11/+11
Created a new triggers::module_t to hold the structure. Also make sure mcontrol_t instances are properly initialized.
2022-03-30mcontrol_match_t -> mcontrol_t::match_tTim Newsome1-6/+6
Made mcontrol_t a class as well.
2022-03-30Move mcontrol_t and mcontrol_match_t into triggersTim Newsome1-36/+7
2022-03-30mcontrol_action_t -> triggers::action_tTim Newsome1-10/+1
These actions are not specific to the mcontrol trigger.
2022-03-30trigger_operation_t -> triggers::operation_tTim Newsome1-4/+5
2022-03-29Split isa_parser_t out of processor.* and into its own file (#955)Rupert Swarbrick1-74/+1
The main motivation for this is that we want to move the ISA parsing logic to run before we even construct a simulator. That's probably a bit nicer if we don't depend on the processor header. It also means that we can stop depending on processor.h in disasm.cc or spike_log_parser.cc (both through disasm.h), which feels a bit cleaner: making sense of an instruction trace shouldn't really require knowledge of the internal state of a processor.
2022-03-16Inline most implicit accesses to fflags/frmAndrew Waterman1-2/+2
2022-03-12Construct an isa_parser_t and pass it to processor_t constructorRupert Swarbrick1-5/+12
This is a minor change, turning processor_t from a child class of isa_parser_t into a class that contains an isa_parser_t as a field. The point is that it is a step toward separating out "configuration" (and ISA string parsing) from processor state. This should be helpful for rejigging things so that we construct more from a supplied device tree.
2022-03-11Incorporate supported privilege levels into isa_parser_t (#940)Rupert Swarbrick1-1/+2
These affect the "max_isa" value (now exposed as get_max_isa()) and feel like they're similar to the other computations done in isa_parser_t.
2022-03-03Change some methods to take a const isa_parser_t (#939)Rupert Swarbrick1-2/+2
No functional change, but this is needed for a following refactor where we're passing it around const.
2022-02-26add missed extensions specified by '--extension' to custom_extensionsWeiwei Li1-1/+1
2022-02-23perf: refine csr accessibility checkingChih-Min Chao1-0/+2
1. support zicntr and zihpm performance extensions zicntr defines the unprivileged cycle/time/instret zihpm defines the unprivileged hpmcounter3-31 2. the accessibility are controlled only by mcounteren/scounteren/hcounteren for access in different privilege modes Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2022-02-18Split out MINSTRET and MCYCLERupert Swarbrick1-0/+1
Before this change, the MCYCLE CSR was just a proxy for MINSTRET. Similarly, CYCLE was a proxy for INSTRET. This models a machine where every instruction takes exactly one cycle to execute. That's not quite precise enough if you want to do cosimulation: there, you're going to want to MCYCLE to actually match the behaviour of your processor (because you need reads from the relevant CSRs to give the expected result). This commit splits the two CSRs, leaving the other proxy relationships unchanged. The code in processor_t::step() which bumps MINSTRET now bumps MCYCLE by the same amount, maintaining the previous behaviour. Of course, now a cosimulation environment can update the value of MCYCLE to fix things up for multi-cycle instructions after they run.
2022-02-18Rename minstret CSR classes to something more generalRupert Swarbrick1-1/+1
No other functional change. This is preparation for a follow-up commit, which will split MINSTRET and MCYCLE (to allow cosimulation environments where the two values might not be equal)
2022-02-17Split Xbitmanip into its proposed component extensions (#918)Rupert Swarbrick1-1/+8
Before this patch, spike just had an "Xbitmanip" extension which covered everything in the proposed bitmanip extension that hadn't been ratified. The problem is that if you want to model (or verify) a processor that targetted just some of the proposed bitmanip extension, you couldn't configure Spike to do that. For example, the lowRISC Ibex processor has several different configurations. The "balanced" configuration targetted Zba, Zbb, Zbs, Zbf and Zbt of the 0.92 spec. With the Zba, Zbb and Zbs ratified, we'll now be able to use an ISA string like rv32imc_Zba_Zbb_Zbs_XZbf_XZbt and Spike will correctly fail to decode instructions like 'bcompress', which would have been decoded with Xbitmanip. This patch adds a new custom extension name for each part of the extension that wasn't fully ratified. These have an 'X' prefix so, for example, the bit permutation instructions that were proposed as Zbp can be found under XZbp. Specifying "Xbitmanip" gets all of these extensions, so its behaviour should be unchanged. Note that the slo(i) / sro(i) instructions have been moved from the proposed Zbb to XZbp. This matches a comment in the Change History section of v0.93 of the bitmanip spec: it seems that the authors forgot to also move them in Table 2.1 (which gives the lists of instructions for each extension). This change won't break anything that currently exists, but it took quite a while to figure out what was going on so I thought I'd leave a breadcrumb trail for the next engineer! The bulk of the patch is just defining some more entries in the isa_extension_t enum and rewriting each of the instructions to depend on the relevant entry. This is mostly a straight textual replacement but it's slightly more complicated for things like the "pack" instruction that are defined by several different proposed extensions.
2022-02-16Merge branch 'plct-cmo-upstream' of https://github.com/plctlab/plct-spike ↵Andrew Waterman1-0/+7
into plctlab-plct-cmo-upstream
2022-01-29add isa string, csr support for cmo extensionsliweiwei1-0/+7
2022-01-27add disas support for zfinx, zdinx and zhinx{min}Weiwei Li1-0/+4
2022-01-26Use unified ISA-string processing in spike-dasm and spikeWeiwei Li1-8/+21
2022-01-06Support RV32E/RV64E base ISAsAndrew Waterman1-9/+12
2022-01-06DRY in illegal-instruction descriptorsAndrew Waterman1-2/+7
2022-01-06DRY in selecting instruction functionsAndrew Waterman1-0/+2
2021-12-07Add 'Zfhmin' extension (#880)Tsukasa #01 (a4lg)1-0/+1
Zfhmin is a subset of Zfh (half-precision IEEE 754 binary16 floating point) extension, consisting only of data transfer and conversion instructions. This commit adds `EXT_ZFHMIN` to `isa_extension_t`, permits "zfhmin" as a multi-letter extension and adjusts feature gate for data transfer / conversion instructions. * FLH / FSH * FMV.X.H / FMV.H.X * FCVT.S.H / FCVT.H.S * FCVT.D.H / FCVT.H.D (if 'D' extension is also present) * FCVT.Q.H / FCVT.H.Q (if 'Q' extension is also present)
2021-10-14Split 'P' to EXT_ZPN and friends (#830)marcfedorow1-0/+4
* Added ZMMUL extension * Splitted P-ext to its zeds * Typo fix
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