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path: root/riscv/processor.h
AgeCommit message (Expand)AuthorFilesLines
2020-07-29rvv: remove isa string zvamoand zvlssegChih-Min Chao1-2/+0
2020-07-29rvv: remove veew/vemul stateChih-Min Chao1-3/+0
2020-07-29rvv: remove slenChih-Min Chao1-2/+2
2020-07-09Implement hypervisor CSRs read/writeAnup Patel1-0/+19
2020-07-08Extend trap classes to pass more informationAnup Patel1-1/+1
2020-07-02commitlog: extend hint bit to record csr accessChih-Min Chao1-1/+1
2020-06-08Fix performance regressionAndrew Waterman1-1/+1
2020-05-28rvv: apply new overlapping and align macroChih-Min Chao1-1/+1
2020-05-28rvv: extenc VU structure to support 0.9 new fieldsChih-Min Chao1-1/+6
2020-05-26Report haltgroup halt cause, per the debug spec. (#473)Tim Newsome1-1/+5
2020-05-10Implement CSR read/write behavior for coarse-grain PMPAndrew Waterman1-0/+2
2020-05-09Support consuming PMP number and granularity from DTBAndrew Waterman1-0/+6
2020-05-09Rename n_pmp constant to max_pmpAndrew Waterman1-3/+3
2020-04-24parser: exhance --isa to support extended extensionChih-Min Chao1-2/+15
2020-03-27Write execution logs to a named log file (#409)Rupert Swarbrick1-3/+9
2020-01-24rvv: remove duplicate vectorUnit declarationChih-Min Chao1-54/+0
2020-01-22commitlog: rvv: change vector register read/write interfaceChih-Min Chao1-0/+59
2020-01-22commitlog: extend reg record to keep multiple accesssChih-Min Chao1-5/+3
2020-01-13commitlog: extend load/store record to keep multiple accessChih-Min Chao1-6/+2
2019-12-20rvv: change vsetvl[i] to match 0.8 specChih-Min Chao1-1/+1
2019-12-20rvv: add quad insn and new vlenb csrChih-Min Chao1-1/+1
2019-12-16extend the commit and memory writes log feature with memory reads (#370)John Ingalls1-0/+1
2019-11-12Add --priv option to control which privilege modes are availableAndrew Waterman1-4/+5
2019-11-11rvv: refine vsetvl[i] logicChih-Min Chao1-1/+1
2019-10-28Implement support for big-endian hostsMarcus Comstedt1-0/+5
2019-09-27Fixed match trigger MATCH_NAPOT case. (#335)fborisovskii1-1/+1
2019-09-18Extends the commit log feature with memory writes. (#324)dave-estes-syzexion1-0/+8
2019-09-18Adds --log-commits commandline option. (#323)dave-estes-syzexion1-0/+3
2019-07-16Writing non-existent CSRs, access FPRs with mstatus.FS=0 (#311)Tim Newsome1-1/+1
2019-07-12Add debug_mode state bit, rather than overloading dcsr.causeAndrew Waterman1-2/+4
2019-06-14rvv: add varch option parser and initialize vector unitChih-Min Chao1-1/+3
2019-06-14rvv: add vector unit structureChih-Min Chao1-0/+118
2018-09-25Add PMP supportAndrew Waterman1-0/+4
2018-07-10Refactor and fix LR/SC implementation (#217)Andrew Waterman1-3/+0
2018-03-21Implement Hauser misa.C misalignment proposal (#187)Andrew Waterman1-1/+4
2018-03-14Fix a bug caused by moving misa into state_t. (#180)Prashanth Mundkur1-1/+1
2018-03-13Move processor.isa to state.misa, since it really belongs there.Prashanth Mundkur1-2/+2
2018-03-06Narrow the interface used by the processors and memory to the top-level simul...Prashanth Mundkur1-4/+5
2018-03-06Fix install of a missed header from debug_rom.Prashanth Mundkur1-1/+1
2018-03-03Implement clearing-misa.C-while-PC-is-misaligned proposalAndrew Waterman1-0/+5
2017-11-27Rename badaddr to tvalAndrew Waterman1-2/+2
2017-11-27Rename sptbr to satpAndrew Waterman1-1/+1
2017-11-09H-mode no longer existsAndrew Waterman1-1/+0
2017-11-09MPP is now WARLAndrew Waterman1-0/+1
2017-10-20Fix commit-log for Q extension, and for RV32 (#143)Andrew Waterman1-1/+9
2017-09-21Fix corner case in repeated execution (#127)Tim Newsome1-0/+3
2017-08-07Fix multicore debug.Tim Newsome1-6/+0
2017-04-18debug: Checkpoint which somewhat works with OpenOCD v13, but still has some b...Megan Wachs1-0/+1
2017-04-17debug: Move things around, but addresses now conflict with ROM.Megan Wachs1-0/+1
2017-04-17Merge remote-tracking branch 'origin/priv-1.10' into HEADMegan Wachs1-6/+5
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