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2019-12-06Require VM enabled for SFENCE.VMA and S-mode for mstatus.SUM (#367)Udit Khanna1-1/+2
* SFENCE.VMA requires S-mode * MSTATUS.SUM hardwired to 0 if no S-Mode
2019-11-27Fix (benign) uninitialized variableAndrew Waterman1-1/+1
2019-11-24Initialize state.misa prior to calls to supports_extensionAndrew Waterman1-0/+2
Partially reverts 0162a6e72421b5cbec1905b4cae7bfab98afe83f Closes #361
2019-11-12mstatus.FS only exists if (S || V || F)Andrew Waterman1-1/+5
2019-11-12Remove S-mode interrupts when S-mode not presentAndrew Waterman1-5/+12
2019-11-12Fix mode-transition logic when S-mode not presentAndrew Waterman1-1/+1
2019-11-12Add --priv option to control which privilege modes are availableAndrew Waterman1-2/+27
2019-11-12Factor out boilerplate strtolower functionAndrew Waterman1-3/+9
2019-11-12In parse_isa_string, populate max_isa rather than state.misaAndrew Waterman1-7/+3
reset will copy max_isa over to state.misa.
2019-11-11rvv: refine vsetvl[i] logicChih-Min Chao1-4/+17
1. fix the ELAN check for vill 2. handle 'rs1 = x0' 3. make logic more readable Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-10-24Initialize histogram_enabled and log_commits_enabled in constructor (#354)Scott Johnson1-0/+1
Otherwise they are left uninitialized and causing bizarre reproducibility problems in my application.
2019-09-18Adds --log-commits commandline option. (#323)dave-estes-syzexion1-0/+13
* Adds --log-commits commandline option. Similar to histogram support, the commit logging feature must be enabled with a configure option: --enable-commitlog. However, unlike that feature, there was no way to turn off the logging with a commandline option once the functionality was built in. This (git) commit provides that abilty. * Changes addressing review feedback.
2019-08-23Remove statement with no effectAndrew Waterman1-1/+0
2019-07-19Set vtype.vill correctly; also reset it to trueAndrew Waterman1-3/+8
Resolves #313
2019-07-19Check presence of V extension when accessing vector CSRsAndrew Waterman1-0/+15
2019-07-19VL and VTYPE aren't writable CSRsAndrew Waterman1-12/+0
2019-07-16Writing non-existent CSRs, access FPRs with mstatus.FS=0 (#311)Tim Newsome1-2/+7
* Don't corrupt s0 when abstract CSR write fails. * Support abstract FPR access then mstatus.FS=0 Discussion on the spec list leans towards this being a requirement. Certainly users want their debugger to be able to access all registers regardless of target state.
2019-07-12Add debug_mode state bit, rather than overloading dcsr.causeAndrew Waterman1-4/+5
In the previous scheme, debug-mode software could exit debug mode by zeroing the dcsr.cause field. While benign, that behavior is out of spec.
2019-07-11Fix support for 32-bit hosts (but no V extension in that case!)Andrew Waterman1-1/+5
2019-07-11Support S-mode vectored interruptsAndrew Waterman1-2/+3
2019-07-05Fix clang uninitialized variable warningAndrew Waterman1-1/+1
2019-06-18rvv: add control instructions and system register accessChih-Min Chao1-0/+31
Signed-off-by: Bruce Hoult <bruce@hoult.org> Signed-off-by: Dave Wen <dave.wen@sifive.com> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-06-14rvv: add varch option parser and initialize vector unitChih-Min Chao1-4/+67
the default vector parameters are defined in configuration time but can be changed throught command-line option Signed-off-by: Dave Wen <dave.wen@sifive.com>
2019-06-14rvv: add vector unit structureChih-Min Chao1-0/+26
Signed-off-by: Bruce Hoult <bruce@hoult.org> Signed-off-by: Dave Wen <dave.wen@sifive.com>
2019-03-30RV32Q is not invalidAndrew Waterman1-3/+0
https://github.com/riscv/riscv-isa-manual/commit/013ba6dc8a504ee4ad7bee42554fecaef7ba797f#diff-2a8fece1cbcdf623cafbce866ea7d4d0R7
2019-03-27Respect interrupt priorities even when not delegatedAndrew Waterman1-9/+13
The spec says that e.g. MEI takes priority over SEI. We got this right in the common case that SEI is delegated to S-mode, but we reversed it in the undelegated case. The destination privilege was correct, so this wasn't much of a problem, but it is technically noncompliant. Resolves #288
2019-02-04Fix use of old name `riscv-isa-run` (#269)Luís Marques1-1/+1
2018-12-21Reserve the PMP R=0 W=1 combinationAndrew Waterman1-2/+5
This was a post-v1.10 amendment to the privileged spec. https://github.com/riscv/riscv-isa-manual/commit/059f64c941856f249d8a0647e23e150dbdb1f62c
2018-10-04Set marchid to assigned value 5Andrew Waterman1-1/+1
https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md TODO: allow Spike users to override marchid/mvendorid/mimpid to mimic their hardware implementations more closely.
2018-09-27Add comment about CSR read side effectsAndrew Waterman1-0/+3
2018-09-25For backwards compatibility, reset PMP to permit all accessesAndrew Waterman1-0/+3
2018-09-25Add PMP supportAndrew Waterman1-0/+32
2018-08-22Make IRQ_COP read-only/undelegable unless coprocessor is presentAndrew Waterman1-1/+2
2018-08-21Instantiate disassembler after max_xlen is knownAndrew Waterman1-1/+5
This fixes RVC disassembly. It's done in a way that doesn't break 2cd60b277e909a5599ca48e4561cbfbc61460186
2018-08-17Don't increment instret immediately after it is written (#231)Andrew Waterman1-0/+6
This brings Spike into compliance with this clause in the spec: https://github.com/riscv/riscv-isa-manual/blob/master/src/csr.tex#L96
2018-07-31Make sstatus.MXR readableAndrew Waterman1-1/+1
h/t @taoliug
2018-07-23Fix using the uninitialized disassemble object. (#220)SeungRyeol Lee1-1/+1
This fixes runtime crash when custom extension registers its disassembly.
2018-07-10Refactor and fix LR/SC implementation (#217)Andrew Waterman1-3/+0
- Use physical addresses to avoid homonym ambiguity (closes #215) - Yield reservation on store-conditional (https://github.com/riscv/riscv-isa-manual/commit/03a5e722fc0fe7b94dd0a49f550ff7b41a63f612) - Don't yield reservation on exceptions (it's no longer required).
2018-05-31Put simif_t declaration in its own file. (#209)Andy Wright1-1/+1
By separating the simif_t declaration from the sim_t declaration, the simif_t declaration no longer depends on fesvr header files. This simplifies compilation of custom sim class implementations that don't depend on fesvr.
2018-03-21Implement Hauser misa.C misalignment proposal (#187)Andrew Waterman1-3/+7
See https://github.com/riscv/riscv-isa-manual/commit/0472bcdd166f45712492829a250e228bb45fa5e7 - Reads of xEPC[1] are masked when RVC is disabled - Writes to MISA are suppressed if they would cause a misaligned fetch - Misaligned PCs no longer need to be checked upon fetch
2018-03-19Fix spike-dasm. (#184)Tim Newsome1-1/+2
It had been broken by 90bafe660b323250338fd564bb9ab4316576d59b.
2018-03-16Implement debug havereset bitsTim Newsome1-0/+2
2018-03-14Fix a bug caused by moving misa into state_t. (#180)Prashanth Mundkur1-2/+3
* Fix misa losing its value in processor constructor due to state:reset() following state.misa initialization. Make state:reset() preserve misa. * Set state.misa to max_isa on reset(). * Idiomatic fix for earlier commit.
2018-03-13Move processor.isa to state.misa, since it really belongs there.Prashanth Mundkur1-8/+8
2018-03-06Narrow the interface used by the processors and memory to the top-level ↵Prashanth Mundkur1-1/+1
simulator/htif. This allows the implementation of an alternative top-level simulator class.
2018-03-03Enforce 2-byte alignment of mepc/sepc/dpcAndrew Waterman1-3/+3
2018-02-13Implement cycleh/instreth CSRs for RV32 (#172)Andrew Waterman1-0/+5
2017-11-27Rename badaddr to tvalAndrew Waterman1-9/+9
2017-11-27Rename sptbr to satpAndrew Waterman1-8/+8
2017-11-27Set tval to 0 on traps with no specified tvalAndrew Waterman1-4/+2
Simply not writing the register was not a conformant implementation.
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