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rocket-tools/riscv-gnu-toolchain/spike.git
confprec
cs250
cycleh
debug_rom
debug_rom_fence
device_flags
dtm_reset_error
dts_parsing
dynamic
eos18-bringup
factor-out-macros
fix-bf16
force-rtti
fp-encoding
heterogeneous_mc
hwachav4
increase-stack-size
itrigger-etrigger-cleanup
load_reservation_set_size
log-commits-faster
master
mmio-hack
mvp
no_progbuf
no_progbuf2
nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
plic-clint-endian
plic_uart_v1
priv-1.10
private-l1-caches
pte-info-and-delegation
remove-tests
rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
sparse-mem
speedup-hacks
static-link
test
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whole-archive
sifive/rvv0.9-phase2
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riscv
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processor.cc
Age
Commit message (
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Author
Files
Lines
2019-11-12
Remove S-mode interrupts when S-mode not present
Andrew Waterman
1
-5
/
+12
2019-11-12
Fix mode-transition logic when S-mode not present
Andrew Waterman
1
-1
/
+1
2019-11-12
Add --priv option to control which privilege modes are available
Andrew Waterman
1
-2
/
+27
2019-11-12
Factor out boilerplate strtolower function
Andrew Waterman
1
-3
/
+9
2019-11-12
In parse_isa_string, populate max_isa rather than state.misa
Andrew Waterman
1
-7
/
+3
2019-11-11
rvv: refine vsetvl[i] logic
Chih-Min Chao
1
-4
/
+17
2019-10-24
Initialize histogram_enabled and log_commits_enabled in constructor (#354)
Scott Johnson
1
-0
/
+1
2019-09-18
Adds --log-commits commandline option. (#323)
dave-estes-syzexion
1
-0
/
+13
2019-08-23
Remove statement with no effect
Andrew Waterman
1
-1
/
+0
2019-07-19
Set vtype.vill correctly; also reset it to true
Andrew Waterman
1
-3
/
+8
2019-07-19
Check presence of V extension when accessing vector CSRs
Andrew Waterman
1
-0
/
+15
2019-07-19
VL and VTYPE aren't writable CSRs
Andrew Waterman
1
-12
/
+0
2019-07-16
Writing non-existent CSRs, access FPRs with mstatus.FS=0 (#311)
Tim Newsome
1
-2
/
+7
2019-07-12
Add debug_mode state bit, rather than overloading dcsr.cause
Andrew Waterman
1
-4
/
+5
2019-07-11
Fix support for 32-bit hosts (but no V extension in that case!)
Andrew Waterman
1
-1
/
+5
2019-07-11
Support S-mode vectored interrupts
Andrew Waterman
1
-2
/
+3
2019-07-05
Fix clang uninitialized variable warning
Andrew Waterman
1
-1
/
+1
2019-06-18
rvv: add control instructions and system register access
Chih-Min Chao
1
-0
/
+31
2019-06-14
rvv: add varch option parser and initialize vector unit
Chih-Min Chao
1
-4
/
+67
2019-06-14
rvv: add vector unit structure
Chih-Min Chao
1
-0
/
+26
2019-03-30
RV32Q is not invalid
Andrew Waterman
1
-3
/
+0
2019-03-27
Respect interrupt priorities even when not delegated
Andrew Waterman
1
-9
/
+13
2019-02-04
Fix use of old name `riscv-isa-run` (#269)
Luís Marques
1
-1
/
+1
2018-12-21
Reserve the PMP R=0 W=1 combination
Andrew Waterman
1
-2
/
+5
2018-10-04
Set marchid to assigned value 5
Andrew Waterman
1
-1
/
+1
2018-09-27
Add comment about CSR read side effects
Andrew Waterman
1
-0
/
+3
2018-09-25
For backwards compatibility, reset PMP to permit all accesses
Andrew Waterman
1
-0
/
+3
2018-09-25
Add PMP support
Andrew Waterman
1
-0
/
+32
2018-08-22
Make IRQ_COP read-only/undelegable unless coprocessor is present
Andrew Waterman
1
-1
/
+2
2018-08-21
Instantiate disassembler after max_xlen is known
Andrew Waterman
1
-1
/
+5
2018-08-17
Don't increment instret immediately after it is written (#231)
Andrew Waterman
1
-0
/
+6
2018-07-31
Make sstatus.MXR readable
Andrew Waterman
1
-1
/
+1
2018-07-23
Fix using the uninitialized disassemble object. (#220)
SeungRyeol Lee
1
-1
/
+1
2018-07-10
Refactor and fix LR/SC implementation (#217)
Andrew Waterman
1
-3
/
+0
2018-05-31
Put simif_t declaration in its own file. (#209)
Andy Wright
1
-1
/
+1
2018-03-21
Implement Hauser misa.C misalignment proposal (#187)
Andrew Waterman
1
-3
/
+7
2018-03-19
Fix spike-dasm. (#184)
Tim Newsome
1
-1
/
+2
2018-03-16
Implement debug havereset bits
Tim Newsome
1
-0
/
+2
2018-03-14
Fix a bug caused by moving misa into state_t. (#180)
Prashanth Mundkur
1
-2
/
+3
2018-03-13
Move processor.isa to state.misa, since it really belongs there.
Prashanth Mundkur
1
-8
/
+8
2018-03-06
Narrow the interface used by the processors and memory to the top-level simul...
Prashanth Mundkur
1
-1
/
+1
2018-03-03
Enforce 2-byte alignment of mepc/sepc/dpc
Andrew Waterman
1
-3
/
+3
2018-02-13
Implement cycleh/instreth CSRs for RV32 (#172)
Andrew Waterman
1
-0
/
+5
2017-11-27
Rename badaddr to tval
Andrew Waterman
1
-9
/
+9
2017-11-27
Rename sptbr to satp
Andrew Waterman
1
-8
/
+8
2017-11-27
Set tval to 0 on traps with no specified tval
Andrew Waterman
1
-4
/
+2
2017-11-20
Implement priv-1.11 interrupt-priority scheme (#161)
Andrew Waterman
1
-1
/
+18
2017-11-09
Remove redundant U/S mode advertisement
Andrew Waterman
1
-4
/
+0
2017-11-09
H-mode no longer exists
Andrew Waterman
1
-1
/
+0
2017-11-09
MPP is now WARL
Andrew Waterman
1
-6
/
+22
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